Hello,
I'm working on a ECP5 project.
I'm using Lattice Diamond 64bit 3.12.1.454 on Windows 10 x64.
I usually write it in Verilog, using LSE as synthesizer.
It happens that I mistype something. Even something simple like a wire without the ending.
When it happens the only error i get on Output tab is something like:
-- Verilog file '___filefullpath___.v' ignored due to errors (VERI-1483)
ERROR - Failed to analyze design file '___filefullpath___.v'.
Done: error code 2
Error, Warning, Info tab does not help.
I'm wondering if there's some setting I can use to enable a higher verbose to catch the error.
Thanks!