Lattice: Low power/High Performance targets?

[drwho9437]

I'm working with a Lattice Certus-Nx right now and it has two target types: low power and high performance in the project definition.

The power mode is mentioned in the datasheet in passing in a few places but not exactly what is configured differently. In my mind it could be route and place or it could be something physical in the chip.

Route and place is easy enough, maybe by placing it in certain areas it can gate the design so certain things are fully off, maybe that makes it bigger or it trades area for speed in some other way that saves power. I don't see applying a different core voltage anywhere so this certainly is an option.

Physically the only thing I can really think of given their is no core voltage change and it seems to be the same part for both "modes" would be a backgate voltage since this is an SOI device, that could trade power for speed.

If I understood how this worked I would understand which mode I really wanted to be in. I haven't found a white paper or anything really explaining the difference. I haven't read every page of the datasheet but I've looked quite a bit.

Anyone know anything?

Edit: I may have answered my own question but will leave this up. I found this in the power management calculation guide

"The Certus-NX, CertusPro-NX, and MachXO5-NX family parts have the ability to switch power performance grades due
to a feature of the 28 nm Fully Depleted Silicon on Insulator (FDSOI) technology. The power-speed tradeoff on the
technology can be modified by adjusting the back bias voltage. This is implemented by choosing one of the two power
performance grades available at each speed and voltage setting. The HP grade stands for high performance, and
consumes the most power. The LP grade stands for low power, and consumes the least power at the cost of speed.
Switching to LP mode can save the static power consumed by the application."

This was one of my guesses and makes sense given how SOI devices work, this implies they have a global back gate that shift the threshold to be be smaller at the cost of higher leakage in performance mode.

[SiliconWizard]

Here is a very short introduction: https://anysilicon.com/fdsoi/

Yes one very simplified way of understanding it is that by adjusting the back bias voltage, you can basically adjust the threshold voltage - and the lower the threshold and potentially the lower the power consumption you can achieve.

Ambiq has taken a different approach they called SPOT: https://ambiq.com/spot/ , which doesn't require FDSOI.
Their MCUs are mind-blowingly low power. No, really.

I haven't used the Certus-NX line yet but would be glad to get feedback on it.

[drwho9437]

I am actually an expert in such things but thanks for the links. I just didn't know what approach they were taking.

I don't know what about this FPGA you would want to know. Radiant is very easy to use. I used to teach students using Quartus II and I used ISE and Vivado also, I think this is probably the easiest IDE I have seen for simple stuff at least. The documentation from Lattice is okay to bad (particularly for the primitives it is very minimal). Power does seem quite low.

I designed my own 8 layer board for the -40/256 ball part but I have been waiting on chips for 9 months now. I managed to find a Rev B dev board which has let me start work. I like the Pro development board more than the PCI-E one I have but Certus-Pro requires a non-free license. If the -40 isn't big enough we might move to the -100 pro if we otherwise like the results. I would assume it is mostly just the die size and nothing to do with the process/layout or anything as that would be way to much work. I didn't look too closely but the -50 pro and the -40 non-pro have similar LUT counts so it is probably hard IP that I don't probably need that is the difference between them, thus it is likely -40 or -100 parts that I would use. Higher I/O count on the Pro could be worth it in some applications I might need as well.

For me the low power nature is kind of a big deal as that is often a major draw back of non-ASIC solutions. That the QFN iCE40 UP is also in the newer Radiant toolchain is nice for some of the most simple glue CPLD like applications I might have as well. I have mostly used smaller FPGAs: Max, Cyclone, Spartan, Artix, Microsemi stuff. So I'm not a huge Virtex takes 800 W FPGA person. I have to use FPGA for fast I/O between analog converters mostly (both ways).