Lattice UltraPlus timing constraint help..

[dpariseau]

I have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior.  I'm pretty sure it's due to timing constraint issues (at present I have no timing constraints implemented).  I'm new to specifying those and so it's a bit daunting to figure out how to resolve these issues.

a) If anyone can point me to a good resource that shows how to arrive at what constraints are needed in a design that would be great.  The syntax and details of implementing the constraints are readily available it's knowing what constraints to specify that's at issue...

b) If anyone has "significant" experience with doing this and wants to make some extra cash looking over my design and helping me work out the constraints to resolve my issues I'd be happy to pay for the help.

c) If anyone has any other ideas that might help, I'm open to them.

Thanks,
Dave.

[SiliconWizard]

Even without explicit timing constraints, the tools will evaluate timing and give you the estimated max frequency at which your design can safely run. Did you take a look at this?

Then, not knowing anything about your design, one thing I can say is that "marginal behavior", if you're certain 1/ that you don't exceed the above max frequency and 2/ that your design is at least behaviorally correct (did you simulate it?), is often due to clock domain crossing issues. If you're not explicitely using two different (and unsynchronized) clocks in your design, the most probable culprit would be that there is some input signal that is asynchronous to your clock, and that you're not correctly resynchronizing before "using" it (metastability issues). So we don't know squat about your design, but here's some food for thought.