Is this LCD module your top heiarchy in your project?
Using this 'really' old style Verilog port definitions, you still need to declare each port name which wires to the outside world by placing it's name inside the 'module xxx( ... )' brackets. Then continue to define if it is an 'output, input, or bidir', then next you may also force some to be a direct register, or wire....
If this is your first Verilog code, then it might be appropriate to learn from scratch slightly more modern port definition practices.
As for on Quartus, if you are using the block-diagram feature and the 'generated symbol' you have shown us, then yes, adding and wiring an 'output', 'input', or 'bidir' pin to your symbol is recommended to allow connections to FPGA pins, or another larger parent sheet or schematic.
I would personally forgo any block diagram schematics and stick to strictly verilog source files and tell Quartus which source file is the top hierarchy whose module's (port names) will become available to assign to FPGA pins after analysis and synthesis.