LCD prj for Altera Cyclon IV do I need to add input/output ports in bsf how

[barnea10]

hi
I use Quartus II 13.1 (64-bit) Web Edition with kit of Altera Cyclon IV and opened an example project for LCD display
in verilog.
I opened the project, the code opened (attached)
compilation pass ok,
and I opened the bsf design file that shows the block and at
the inputs and outputs appear X
so I thought I should add input port and output port and also ALTPLL for CLK
how ever where I try to insert a port but It is not working
what am I missing ?
thanks !

Code: [Select]


module lcd(clk, rs, rw, en,dat); 
input clk; 
 output [7:0] dat;
 output  rs,rw,en;
 //tri en;
 reg e;
 reg [7:0] dat;
 reg rs;   
 reg  [15:0] counter;
 reg [4:0] current,next;
 reg clkr;
 reg [1:0] cnt;
 parameter  set0=4'h0;
 parameter  set1=4'h1;
 parameter  set2=4'h2;
 parameter  set3=4'h3;
 parameter  dat0=4'h4;
 parameter  dat1=4'h5;
 parameter  dat2=4'h6;
 parameter  dat3=4'h7;
 parameter  dat4=4'h8;
 parameter  dat5=4'h9;

 parameter  dat6=4'hA;
 parameter  dat7=4'hB;
 parameter  dat8=4'hC;
 parameter  dat9=4'hD;
 parameter  dat10=4'hE;
 parameter  dat11=5'h10;
 parameter  nul=4'hF;
always @(posedge clk)     
 begin
  counter=counter+1;
  if(counter==16'h000f) 
  clkr=~clkr;
end
always @(posedge clkr)
begin
 current=next;
  case(current)
    set0:   begin  rs<=0; dat<=8'h30; next<=set1; end
    set1:   begin  rs<=0; dat<=8'h0c; next<=set2; end
    set2:   begin  rs<=0; dat<=8'h6; next<=set3; end
    set3:   begin  rs<=0; dat<=8'h1; next<=dat0; end
    dat0:   begin  rs<=1; dat<="H"; next<=dat1; end
    dat1:   begin  rs<=1; dat<="E"; next<=dat2; end
    dat2:   begin  rs<=1; dat<="L"; next<=dat3; end
    dat3:   begin  rs<=1; dat<="L"; next<=dat4; end
    dat4:   begin  rs<=1; dat<="O"; next<=dat5; end
    dat5:   begin  rs<=1; dat<=" "; next<=dat6; end

    dat6:   begin  rs<=1; dat<="W"; next<=dat7; end
    dat7:   begin  rs<=1; dat<="O"; next<=dat8; end
    dat8:   begin  rs<=1; dat<="R"; next<=dat9; end
    dat9:   begin  rs<=1; dat<="L"; next<=dat10; end
    dat10:   begin  rs<=1; dat<="D"; next<=dat11; end
    dat11:   begin  rs<=1; dat<="!"; next<=nul; end
     nul:   begin rs<=0;  dat<=8'h00;                   
              if(cnt!=2'h2) 
                  begin 
                       e<=0;next<=set0;cnt<=cnt+1; 
                  end 
                   else 
                     begin next<=nul; e<=1;
                    end   
              end
   default:   next=set0;
    endcase
 end
assign en=clkr|e;
assign rw=0;
endmodule 


[BrianHG]

Is this LCD module your top heiarchy in your project?

Using this 'really' old style Verilog port definitions, you still need to declare each port name  which wires to the outside world by placing it's name inside the 'module xxx( ... )' brackets.  Then continue to define if it is an 'output, input, or bidir', then next you may also force some to be a direct register, or wire....

If this is your first Verilog code, then it might be appropriate to learn from scratch slightly more modern port definition practices.

As for on Quartus, if you are using the block-diagram feature and the 'generated symbol' you have shown us, then yes, adding and wiring an 'output', 'input', or 'bidir' pin to your symbol is recommended to allow connections to FPGA pins, or another larger parent sheet or schematic.

I would personally forgo any block diagram schematics and stick to strictly verilog source files and tell Quartus which source file is the top hierarchy whose module's (port names) will become available to assign to FPGA pins after analysis and synthesis.

[c64]

What is top entity of the project? If it's verilog file, you don't need to add ports.

If it's bdf, you need to add ports from the toolbar. You say it's not working. What happens when you try to add them?

[barnea10]

thanks
its Verilog, ill check again