I'm looking at implemented LPDCs in an FPGA. Here's what Wikipedia has to say about LDPC:
a low-density parity-check (LDPC) code is a linear error correcting code, a method of transmitting a message over a noisy transmission channel. ... LDPC codes are capacity-approaching codes, which means that practical constructions exist that allow the noise threshold to be set very close to the theoretical maximum (the Shannon limit) for a symmetric memoryless channel.
They are becoming pretty ubiquitous - DVB, Satellite Comms, WiFi and so on.
I found the math behind LDPC decoding pretty hard to get to grips with. Log likelihoods, and working with the products and sums of hyperbolic tangents was all beyond my understanding when I started. The area is very rich in research, and authors always assume that you understand the basics. So finding an understandable way to get a foot in the door is hard. The best introduction to LDPC codes I've found is this paper, as it has a fully worked example you can follow along with.
https://www.researchgate.net/publication/228977165_Introducing_Low-Density_Parity-Check_CodesTo make sure that my understanding of the math is correct, I made a small bit of code that mirrors the fully worked example Sum Product decoder, and lets you play with the numbers interactively:
https://github.com/hamsternz/LDPC_demoHopefully if others have to make the same journey as me it will help them clarify what exactly is going on!