Electronics > FPGA

LFSR toggle rate?


I am using a LFSR that toggles one DFFs per clock cycle.

Does this mean the toggle rate is:

=1/total number of DFFs

I am using a power estimation tool to figure out the dynamic power consumption.

Unless something is unusual about it, all of the DFFs in the LFSR will toggle each clock cycle, unless you are gating the clock somehow.

Depends on the input though, if it is just passing a 1, then only 1 DFF should toggle each clock cycle as it passes through the chain.

I would hope that the XOR terms are clocked as well.  Otherwise the chain is simply a shift register.

Every schematic of an LFSR I have ever seen has all flops clocked simultaneously.  I suppose it could be done some other way but why?

Additional thought.

I suppose what the OP means by "a DFF not toggling" is that its output doesn't change state on a given clock cycle.
I won't get into the implementation of a LFSR, but I'll just elaborate on the above point.

Since, as someone said above, in a typical FPGA, all DFFs in your design (except if you managed to explicitely clock gate them, which is either not exactly possible or not guaranteed depending on said FPGA) will be clocked, what matters here IMO is down to the number of transistors that make up a DFF, and the number of them that will switch even when the output doesn't change state. You can refer to this basic design: https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#/media/File:True_single-phase_edge-triggered_flip-flop_with_reset.svg for starters.


[0] Message Index

There was an error while thanking
Go to full version