Electronics > FPGA

LFSR

(1/5) > >>

NivagSwerdna:
I'm about to embark on my first FPGA project and have decided on verilog...

So one of the first things I have to build is a LFSR where various taps combine to feedback...

This got me thinking...

If the LSFR is represented by a series of flip flops each feeding each other and sharing a common clock with the input either the output of the previous gate or a combinatorial function of various prior taps...

Is this inevitably a race condition because the inputs are based on the outputs which change at the same clock edge?

I have seen code like...

out <= { out[6:0], feedback }

Does that guarantee that it works atomically even when feedback is derived from the values of out on the RHS?

Maybe I am overthinking this?

Thanks in advance

AndyC_772:
No, it's OK - this is why vendors' synthesis tools are used.

I speak VHDL, not Verilog, but the basic premise is the same - in synchronous logic, any reference to the state of a signal means the state of that signal at the instant just before the active clock edge.

The synthesis tool contains a timing model of the FPGA, which the manufacturer guarantees across voltage, temperature and part-to-part variation. Provided the tool's timing analyser indicates positive setup & hold slack, you compile your code for the correct variant of the device, and you use that device within the manufacturer's recommended spec, then your design will meet timing.

In more complex designs - especially those with multiple clocks - then you do need to very carefully consider how signals cross clock domains, and you must create a timing constraints file (.SDC) which describes the relationships between your clocks and other important signals. Some people make a career out of this.

Incidentally, it's also why open source FPGA tools aren't really a thing. There have been a few attempts, but in the absence of a guaranteed (proprietary) timing model for the device, there's no way to ensure that setup times are met at any particular clock frequency, or that hold times are met at all.

NivagSwerdna:
That's interesting. So there is a contract in there somewhere where the LHS relies on the RHS being fixed at some time and the subsequent assignment propagating to the LHS.

I don't know how a FF with feedback actually guarantees this behaviour but it must do otherwise shift registers wouldn't work!

In my example above the feedback is derived by a continuous net assignment ..

E.g.

feedback = out[0] ^ out[2]

Which gives an interesting mix of combinatorial and sequential in the assignment of the register.

This is obviously a trivial case but it is interesting that you mention the implicit rules being applied to the synthesis... I guess I have a lot to learn.

Thanks

AndyC_772:
There's really two parts to this.

Firstly, you need to be able to write code that has a clear, well defined, guaranteed meaning, and that's down to the language itself.

Second, this has to be physically implemented in a way that behaves as per your intent. This is down to causality; a signal cannot, in practice, change until some time after a clock edge has been received. Every logic gate, and the connections between its output and any inputs to other gates (including itself), takes time to switch state because of parasitic capacitance. This, helpfully, guarantees that the input to a gate won't change until *after* a clock has been received, provided the clock itself isn't delayed.

FPGAs contain global clock nets, hard wired into the silicon, for this very reason. It helps ensure that every logic cell gets a clock at more or less the same time, and the data inputs change later - by which time these inputs have already been latched.

langwadt:

--- Quote from: NivagSwerdna on May 17, 2022, 11:33:36 am ---That's interesting. So there is a contract in there somewhere where the LHS relies on the RHS being fixed at some time and the subsequent assignment propagating to the LHS.

I don't know how a FF with feedback actually guarantees this behaviour but it must do otherwise shift registers wouldn't work!

In my example above the feedback is derived by a continuous net assignment ..

E.g.

feedback = out[0] ^ out[2]

Which gives an interesting mix of combinatorial and sequential in the assignment of the register.

This is obviously a trivial case but it is interesting that you mention the implicit rules being applied to the synthesis... I guess I have a lot to learn.

Thanks

--- End quote ---


the simplest explanation is that nothing can happen instantly, so an FF output cannot change until some time after the clock edge, reacting on what the input was right before the clock edge

 

Navigation

[0] Message Index

[#] Next page