Author Topic: Low budget FPGA needed  (Read 11153 times)

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Offline rfspeziTopic starter

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Re: Low budget FPGA needed
« Reply #75 on: August 17, 2023, 09:22:48 pm »
but then you have to sample and store the full frame for both streams, much more efficient to do the match at a higher rate and then only store the bits you know are in the middle of the datastream

I am not sure if the complexity is worth it since the streams are buffered and analyzed in an companion cpu anyway.
I want to keep the FPGA complexity as low as possible beeing able to use a really cheap one.
« Last Edit: August 17, 2023, 09:27:25 pm by rfspezi »
 

Offline langwadt

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Re: Low budget FPGA needed
« Reply #76 on: August 17, 2023, 09:49:23 pm »
but then you have to sample and store the full frame for both streams, much more efficient to do the match at a higher rate and then only store the bits you know are in the middle of the datastream

I am not sure if the complexity is worth it since the streams are buffered and analyzed in an companion cpu anyway.
I want to keep the FPGA complexity as low as possible beeing able to use a really cheap one.

beginning to sound more and more like an XY problem

do you actually have 16 separate streams or is just 16 phase shifted copies of the same stream and 16 comparators is your attempt at finding the right one?

so you really just need to sync and extract the data from a single stream?



 

Offline PCB.Wiz

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Re: Low budget FPGA needed
« Reply #77 on: August 17, 2023, 11:16:21 pm »
I am not sure if the complexity is worth it since the streams are buffered and analyzed in an companion cpu anyway.
I want to keep the FPGA complexity as low as possible beeing able to use a really cheap one.
An extreme version of that approach, would be to use a couple of jelly bean MCU's to do parallel to serial capture, at 2Msps -> 16 MHz SPI for 8 wide sample. Plenty can manage that.
You might even find a better one that can do 2Msps x 16b -> 32MHz SPI, if you companion cpu manages 32MHz SPI  ?
Then all your 'buffered and analyzed' is moved to your companion cpu - more CPU resource needed, but super cheap and simple capture.
 

Offline gnuarm

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Re: Low budget FPGA needed
« Reply #78 on: August 18, 2023, 12:03:51 am »
I often design in a debugging port, just for this purpose.  It can work great.  If you have to worry about introducing timing errors in your FPGA, you don't understand how timing is handled in FPGA design.  You should never work with FPGAs.   
Yes I do understand how timing is handled in FPGA designs. Hence why I know that sometimes an extra connection can mess up the placement & routing, because I've seen this happened multiple times. And the higher is your clock frequency, the more likely you are to see this problem, especially if you want to "debug" high-fanout nets.

Then, you should know how to detect the timing problem, and how to fix it. 

Are you just trying to be difficult?  What is your point?

that if you are pushing utilization and/or performance adding a connection might make it impossible to meet timing ...

Ok, you win the "Raising Virtually Impossibly Unlikely Problems" award. 
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Offline fourfathom

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Re: Low budget FPGA needed
« Reply #79 on: August 18, 2023, 12:04:04 am »

I am confident, that 2x oversampling in combination with the following constellation will do the job just fine.

-) Short frames (standard clock drift does not matter)
-) Low datarate
-) Long sync pattern
-) Enhanced CRC

3x oversampling could be used for redundancy/sanity check.
However it adds unnecessary cost.

No, 2X sampling will not be reliable, unless you are willing to discard bad-CRC frames.  There will be a one clock-period ambiguity in the detection of the input transition, so where do you put the sample-point?  It could end up anywhere between the data mid-point and on top of the next data transition.

Clock drift (and jitter) *always* matter, there is no escaping this fact.  And not just the receive clock, there's also the transmit clock and noise on the data signal.  All of these add to the sampling uncertainty.

I'm seeing lots of complicated suggestions, just to avoid using a faster sampling clock.  A 32X clock doesn't mean a 32X increase in gatecount.  You have a little more complexity at the input (but not much), and some extra circuitry for the clock-enable controls, but the final result is likely to be simpler.

Yes, you could probably do this is a uController, but this job would be easy in a small to medium low-cost FPGA.  And 32 MHz is *not* fast for a modern FPGA.  With 16 inputs of 1Mbit/s I would be tempted to run the internal clock at 64 MHz, letting me have a single datapath, and shared resources for the 16 channels.  If I thought about it more I could probably reduce the clock rate and still have a single shared datapath...  But 64 MHz is still easy.

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Offline dietert1

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Re: Low budget FPGA needed
« Reply #80 on: August 18, 2023, 05:38:46 am »
For asynchronous input most people use a digital low pass filter to avoid metastability and noise issues. This filter uses oversampling. Oversampling ratio can be configurable. Clock recovery also needs oversampling. Clock recovery means initial determination and then tracking of incoming data clock phase.
If the OP wants to determine initial clock phase by sync pattern matching: In order to guarantee some phase margin, one needs more than one match. If one finds 3x consecutive pattern matches one can select the middle one. A modern FPGA also implements 48 bit or 64 bit shift registers.

Regards, Dieter
« Last Edit: August 18, 2023, 07:03:36 am by dietert1 »
 

Offline mikeselectricstuff

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Re: Low budget FPGA needed
« Reply #81 on: August 18, 2023, 09:44:40 am »
3x oversampling could be used for redundancy/sanity check.
However it adds unnecessary cost.
I doubt it would add any noticeable cost as you have plenty of bandwidth for a 1Mbit stream, and may actually end up smaller/simpler as it's easier to determine framing if you have more samples to play with.
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Offline Canis Dirus Leidy

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Re: Low budget FPGA needed
« Reply #82 on: September 06, 2023, 08:03:26 pm »
2. Whatever comes with the vendor tools. From the really free ones, I use iverilog, but that's only for Verilog. No idea what exists for VHDL.
GHDL. Good enough if gate-level simulation isn't required and vendor (or propiertary) IP blocks aren't used.[1] Plus it can be used for syntax checking by editors like Emacs.

1. Well, there is example of using it with Xilinx Unisym library, but I have not come across detailed descriptions and manuals.
 

Offline bywqdq

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Re: Low budget FPGA needed
« Reply #83 on: November 14, 2023, 02:52:10 am »
AG1K, which is cheap in China, only costs about $1
 

Online up8051

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Re: Low budget FPGA needed
« Reply #84 on: November 16, 2023, 08:47:47 am »
AG1K, which is cheap in China, only costs about $1

More interesting is AGM AG6K SoC but where to by it?

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Offline colorado.rob

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Re: Low budget FPGA needed
« Reply #85 on: November 16, 2023, 09:03:13 pm »
AG1K, which is cheap in China, only costs about $1
Where can these be found outside of China?
 


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