Electronics > FPGA

Low input frequency (1MHz) multiplication via PLL

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BrianHG:

--- Quote from: deanclaxton on June 12, 2021, 06:32:14 am ---
--- Quote from: BrianHG on June 09, 2021, 07:42:46 pm ---@deanclaxton, where did you get that 1.027MHz from.  Is it some old crystal clock?  Or, did you measure the frequency with a scope, or a frequency counter?

Also, if any of those FPGA's can lock onto 2.054MHz directly, with 2 additional inputs, and an inductor/cap/resistor, you can double the 1.027MHz using an async XOR gate programmed into the FPGA.

--- End quote ---

System is an Apple ][ computer, and I'm working on an accelerator with some other features including ROMX functionality (theromexchange.com). The the machine uses a 14.31818MHz reference, that is divided down by 14 to create the CPU clock. NTSC units use that reference anyway - PAL units are slightly different which is why I'd love to be able to do this without an external reference oscillator as I'd possible have to produce the board with 2 different crystals. Perhaps the reprogrammable MEMs oscillators could work for this though.

I'm waiting for the MachXO2 board to arrive and I'll then cobble together a test system :)

--- End quote ---
Why didn't you say so... 1.027 is not the frequency by a mile.  This is why I cannot figure out what you were trying to achieve.   The real frequency is 1.022727271 MHz.....

NTSC and PAL do have a common thread frequency which you can PLL divide perfectly between the two.  It is 27MHz.

The conversion factor is x35/66.  27.0000 * 35/66 = dead perfect 4x NTSC color burst frequency.
I don't remember the PAL factors, but they are also a perfect small integer multiply/divide.

This is why once digital broadcast TV came about, the Analog encoder/decoders used 27MHz crystals so they may support NTSC & PAL with the same clock source.

Now, 35/66 might not be possible with all FPGA PLLs as the numbers are sorta large, however from experience, Altera PLLs can handle it.

In fact, 27x10, 270MHz source clock, divide that by 264 exact and you get 1.02272727MHz exact...

deanclaxton:

--- Quote from: BrianHG on June 12, 2021, 01:36:29 pm ---
--- Quote from: deanclaxton on June 12, 2021, 06:32:14 am ---
--- Quote from: BrianHG on June 09, 2021, 07:42:46 pm ---@deanclaxton, where did you get that 1.027MHz from.  Is it some old crystal clock?  Or, did you measure the frequency with a scope, or a frequency counter?

Also, if any of those FPGA's can lock onto 2.054MHz directly, with 2 additional inputs, and an inductor/cap/resistor, you can double the 1.027MHz using an async XOR gate programmed into the FPGA.

--- End quote ---

System is an Apple ][ computer, and I'm working on an accelerator with some other features including ROMX functionality (theromexchange.com). The the machine uses a 14.31818MHz reference, that is divided down by 14 to create the CPU clock. NTSC units use that reference anyway - PAL units are slightly different which is why I'd love to be able to do this without an external reference oscillator as I'd possible have to produce the board with 2 different crystals. Perhaps the reprogrammable MEMs oscillators could work for this though.

I'm waiting for the MachXO2 board to arrive and I'll then cobble together a test system :)

--- End quote ---
Why didn't you say so... 1.027 is not the frequency by a mile.  This is why I cannot figure out what you were trying to achieve.   The real frequency is 1.022727271 MHz.....

NTSC and PAL do have a common thread frequency which you can PLL divide perfectly between the two.  It is 27MHz.

The conversion factor is x35/66.  27.0000 * 35/66 = dead perfect 4x NTSC color burst frequency.
I don't remember the PAL factors, but they are also a perfect small integer multiply/divide.

This is why once digital broadcast TV came about, the Analog encoder/decoders used 27MHz crystals so they may support NTSC & PAL with the same clock source.

Now, 35/66 might not be possible with all FPGA PLLs as the numbers are sorta large, however from experience, Altera PLLs can handle it.

In fact, 27x10, 270MHz source clock, divide that by 264 exact and you get 1.02272727MHz exact...

--- End quote ---

ah yes - doh! 1.02272727 - thats what I need. 27MHz - nice - multiply x 10, divide by 264 - excellent :) I'll definitely look into that a bit more with the PAL side of things. So the source clock on the motherboard will be running at 1.0227 MHz, and my cpu will be running much faster but synching certain data with the logic on the motherboard. Early days with just a half baked conceptual layout at this stage - FPGA kit should arrive during the week. Previously Id been using using WinCUPL with the Microchip AFT150x CPLD's so will now learn Verilog :)

BrianHG:

--- Quote ---Almost everything in the computer, including some > > peripherals like the floppy controller, are carefully designed ... All the standard Apple II clock frequencies are derived from this. ... (For PAL models, it is 14.25 MHz / 14 = 1.0178571429.
--- End quote ---

Google is your friend... 'pal apple II computer clock frequency'

Switch to 13.5MHz, IE 27MHz/2.  Still a standard, or some PLLs allow you to divide your source clock by 2.

For NTSC, x20, divide by 264 = 1.02272727 MHz perfect.
For NTSC, x35, divide by 462 = 1.02272727 MHz perfect.
For PAL,   x19, divide by 252 = 1.0178571429 MHz perfect

Or,
For NTSC x35, divide by 33 = 14.3181818181818181... MHz perfect.
For PAL,   x19, divide by 18 = 14.25 MHz perfect.

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