Electronics > FPGA

Low input frequency (1MHz) multiplication via PLL

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deanclaxton:
I'm looking to use an FPGA for an upcoming project (my first FPGA project), and am curious about the PLL features. I will have a 1.027MHz clock input that I would like to be able to scale up by 1 to 14x. In theory the PLL resources seem ideal for this (I'm looking at Lattice ICE40 or MachXO2 at this stage since they appear to be well priced) however from the datasheet it appears that they can't handle such a low input frequency. This seems to be common with other standalone PLL clock buffer/multiplier solutions also - many have a minimum input frequency of 2MHz and a minimum output frequency of 10MHz.

In the case of MachXO2 the minimum input frequency is 7MHz, but it can actually divide down into the 10KHz range which is pretty neat.

So it seems that I probably need to use an external oscillator that is 14.3818MHz, and divide that down for my clock, but I'd like to phase match the divided output with the original 1.027MHz clock.

Or is there a better way to approach this? I have yet to decide on the actual FPGA I'll use, so don't yet have a dev board to test myself if it will work via the PLLs.

If anyone has any experience with this I'd be grateful for any advice that can be offered.

Cheers,
Dean

KrudyZ:
Yes this is a rather annoying limitation.
What you could do if you have a fixed input frequency is to start with a higher clock rate and then divide that down to the same or close enough frequency and do a phase comparison. The MACHXO2 has a feature to phase shift its VCO, so you can lock onto a reference if it's within a reasonable range. The resulting clock will have some significant jitter though which you can improve on by running it through a second PLL

BrianHG:

--- Quote from: deanclaxton on June 06, 2021, 10:24:59 am ---So it seems that I probably need to use an external oscillator that is 14.3818MHz, and divide that down for my clock, but I'd like to phase match the divided output with the original 1.027MHz clock.

--- End quote ---

We have done this trick before in an Altera Cyclone by running 1 PLL from a reference, IE 14.31818MHz, bumping it up to a high frequency, IE 14.31818MHz * 32 = 458.18176MHz, then use normal gates to divide down and logically PLL lock onto your 1.027MHz.  Or in our case, it was a 15KHz H-Sync from a video signal which we needed to lock onto for video grabbing to create a new pixel clock.  We took the logic clock output and feed it to the second PLL just to make a new extra clean video clock & to run logic in the FPGA.

The source is somewhere here on EEVBlog, but in the projects section...

Miti:
Here it is

https://www.eevblog.com/forum/projects/modern-equivalent-of-74hc4046-pll/

deanclaxton:
Awesome - I'll look into this further and pick up a MachXO2 dev board to play around with. ICE40 is a contender also, though it doesnt support the low output frequencies on the PLL's so perhaps MachXO2 is the way to go for now. Although it seems that rather than using the PLL to divide down, Id be using gates. I can experiment with both approaches. Its the phase lock I'll have to work out - will do some reading :)

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