low-jitter timing generation using FPGA

[bonelli]

Hello,

I'm trying to generate accurate timings using a FPGA, I'm looking for something like that:

- 3.3V input trigger (SMA connector, 50 ohm matched)
- 2 outputs, respectively delayed with T1/T2 from the rising edge of the trigger
- A serial port to set T1/T2
- A 10MHz TCXO as stable and accurate clock source
- Ideally, (T2-T1), T1 and T2 range from 1ns to µsecs, with ns resolution and <200ps jitter

Basically, I have implemented 2 counters, one for each output. I have 2 cascaded flip-flop to resync the input trigger to the local clock, meaning 2Tcy of jitter. Using a 500MHz clock, the resulting jitter is 4ns, very bad for my application. The 500MHz comes from the PLL of the FPGA, clocked with the 10MHz TCXO.

I'm planning to use all 4 phase-shifted outputs of the PLL, clocking 4 implementations of my counters, to reduce the jitter to 1ns (still bad but better). For each output, I suppose I can OR the output of each phase-delayed counter (using pure combinational circuits).

If the FPGA has multiples PLL, I suppose I can use them all to play with delays and clock more than 4 counters.

But is this approach good? To keep synchronization to the clock (excluding combinational delay loops), I don't see any other way to do the job.

Any advice and ideas appreciated 
Many thanks

[RoGeorge]

I'll be tempted to use tapped delay lines.  Googled for "FPGA ns programmable delay", didn't went into detailed reading, but by their specs the papers seem applicable.  See if any of these design ideas applies to your application:

• A programmable delay line
• Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration
• A high-resolution programmable Vernier delay generator based on carry chains in FPGA
• Non-blocking programmable delay line with minimal dead time and tens of
  picoseconds jitter

[BrianHG]

Using a 500MHz clock, the resulting jitter is 4ns, very bad for my application. The 500MHz comes from the PLL of the FPGA, clocked with the 10MHz TCXO.

You should be achieving 2ns jitter.  If you use a DDR output, sampling your input trigger with a DDR input and storing which clk phase the transition came in on, and using that phase as a reference when driving your DDR output, you should achieve 1ns jitter.  IE: only 1 counter needed, you just need to store which internal CLK phase the source trigger came in on to know which phase you want to drive the output on.

Using LVDS multi-GHZ receivers and transmitters doing the same trick, but x# of bits wide, you can further refine that bleeding edge jitter down to 200ps with 5GHz transceivers.

The other choice is using separate external true VCXOs.  TI has their CDCE9xx series VCXO programable PLL clock generators which run from a single crystal.  Though a mess of parts and wiring for multiple channels, you can potentially get down to below 200ps refinement without such fast PLD IOs.