MachXO2 FIFO_DC - are clocks really independent?

[ataradov]

MachXO2 family has FIFO_DC (First In First Out Dual Clock) primitive. As the name suggests, it has separate read and write clocks.

I can't find a confirmation anywhere that those clocks are really independent or they can only be derived from the same clock.

So the question is - is this FIFO really dual clock, so it can be used for cross clock domain transfer of data? Anyone has any experience or pointers to the documentation I missed?

[SiliconWizard]

I have completed a few projects using a MachXO2, so I'd think I have significant experience with it.
But... I've never actually used FIFO_DC for clock domain crossing on MachXO2 (I have used True dual port memory for this, and it sure worked.)

Reading back the documentation, I can see why you'd be confused. I agree: it's absolutely not clear. I can just say that I'd be very surprised if the "dual-clock FIFO" didn't support clocks on separate domains. But yeah, the docs are pure mess.

[ataradov]

I'll do a test project later today. I have everything setup with a soft cross-domain FIFO, so I'll just replace that. And the project transfers gigabytes of data, so if there are any issues, they will be obvious. I'll report back.

[ataradov]

It does look like it is a real dual clock FIFO. I tested with 120 MHz (PLL output multiplied from CMOS oscillator) and 133 MHz (internal RC) source clock and 30 MHz target clock (from a different CMOS oscillator). I transferred over 60 GB of random data for both clock configurations with no errors.

This is a nice thing to have. It just eliminated a custom cross domain FIFO and simplified design quite a bit.

EDIT: In one of the documents there is an indirect confirmation: "Another clock latency is added due to the clock domain transfer from write clock to read clock using another register which is clocked by read clock that is enabled by read enable."

And now that 133 MHz -> 30 MHz transferred over 250 GB, it is well confirmed.

[fourfathom]

I've used the MachX02 DC FIFO, where one clock is the internal PLL running at 100 MHz and synched to an external 10 MHz reference, and the other is the internal clock generator running at 16 MHz.  Works great.