Max10 JTAG header ???

[lawrence11]

https://forums.intel.com/s/question/0D50P00003yyK4ASAU/max-10-jtag-voltage-question?language=fr

This post pretty much sums up my questionning, I wonder

My setup/voltage from my board is like this, like on this jpeg: I have a terasic probe I intend to use, wich will be connected to my PC, the ribbon is about 7 inches long but I can get a shorter one. The distance from the FPGA pins to the header is about 20mm. Am I safe ? If not what circuit/part exactly I need to add to my board?

Here is a quote from the last post of that forum...

Quote: " Back to the basics. The schematic in post# 1 makes no sense, the relevant point for possible JTAG overshoot is the USB cable supply voltage, not the pull-up resistor voltage. You have JTAG connector pin 4 connected to 3.3V, this might, if at all, be causing overshoot problems with long JTAG traces. The suggestion in the MAX 10 Design Guidelines is to power the USB cable with 2.5V  ?? How ??, consequently the pull-up resistors will be connected to the same voltage.As previously stated, I won't provide an additional 2.5V supply in a single supply MAX 10 design (unless it's used for other purposes, e.g. LVDS IO). I prefer silicon or schottky clamp diodes for the JTAG port, e.g. one of the popular 6-pin ESD protection diode networks."  Have an example?? I hate it when people act all snarky like this.

[ataradov]

I worked with MAX10s quite a bit and I just connect all pull-ups to 3.3 V. As far as I can see everyone does it this way.

I would not worry about overshoots at all. Even if they happen, they don't kill the device instantly, it is more resilient than this. And in production devices JTAG will only be used once, so it should not be a problem.

PS: I only worked with a single supply version of the devices. There may be some critical differences in dual supply devices, but I really don't think so.

[SiliconWizard]

I didn't get what this overshoot on the 3.3V supply was exactly all about?

If you get significant overshoot on a 3.3V locally-regulated supply, then your regulator is shitty, or not used properly. And there are still means of mitigating this.

Now I didn't get how the whole thing was powered, nor what powering the USB cable at 2.5V meant. What's this matter with the USB cable? Is it providing directly the 3.3V supply? Is an USB cable used as a JTAG cable, and not as a proper USB cable?

[ataradov]

No, they mean that overshot on the JTAG lines running at 3.3 V may push the total voltage out of the spec. Altera has some strong words around this in their documents.  But that's probably just liability protection on their part. Those pins are no different than pins on any other device, they can take quite a bit of abuse.

[lawrence11]

Alex, once again, you have provided tremendous insight in a few sentences.

For the past year or so, your simple comments have unstuck me in moments when even google is not enough.

For that I commend you 

[ataradov]

BTW, I have published a schematic of a pretty minimal breakout board for the MAX10 here https://github.com/ataradov/max10_bb

This basic design was also used on multiple other boards without any issue.

[lawrence11]

Ahhh thank you.

But just to be clear on the voltage level that will come out of the terasic board's programming signals, will those be 3.3volt or 5 volt?? I think Im pretty Ok with just not disconnecting the jtag while its  sending signals, since my traces are pretty short I dont expect reflection, and I'll get a shorter ribbon just to be sure, I am not bothered by anything.

[SiliconWizard]

No, they mean that overshot on the JTAG lines running at 3.3 V may push the total voltage out of the spec. Altera has some strong words around this in their documents.  But that's probably just liability protection on their part. Those pins are no different than pins on any other device, they can take quite a bit of abuse.

Oh, OK!
So yeah that's pretty much the same as in ANY case where you have digital signals across a cable... (the USB cable part was kind of confusing though, is it used as a JTAG cable? because otherwise, I still don't get the 2.5V. Are they implying to actually supply 2.5V so that the 3.3V regulator will just NOT regulate? Atrocious if so, but I may again not have gotten this cable thing.)

Dang, if you needed to under-supply your boards to use them with cables, I think you'd have a large problem.

And yes you can always protect individual pins with series resistors (as long as the signal integrity is not compromised). I would also add ESD diodes (TVS) for good measure. I'd be more afraid of ESD when plugging and unplugging cables than with transient overshoot.

[ataradov]

It would depend on the specific board, of curse, but I'm pretty no modern FPGA board  will have 5V anything past the USB supply voltage.

What disconnection are you talking about? Are you planning on programming a custom board using terasic kit? Are you sure it actually has properly exposed JTAG for programming external parts?

[ataradov]

So yeah that's pretty much the same as in ANY case where you have digital signals across a cable... (the USB cable part was kind of confusing though, is it used as a JTAG cable? because otherwise, I still don't get the 2.5V. Are they implying to actually supply 2.5V so that the 3.3V regulator will just NOT regulate? Atrocious if so, but I may again not have gotten this cable thing.)

I think they mean that you should run JTAG interface at 2.5 V, so that even if there is overshoot, it won't exceed 3.3 V.

Intel documents are too detailed. It is good for getting the information you need, but apparently too much information makes people overthink things.

Just run the JTAG at the same voltage as the corresponding FPGA bank and you will be fine. Don't overthink it.

[lawrence11]

This is a board I made, everything is +3.3 volt. I ordered a pcb but then I got tired or soldering tiny ires everywhere due to mistakes.

No I wanna make it right, the second time.

If I need to send a voltage to the terasic usb blaster , it will be +3.3 volt.

the only 5 volt on my board is before the regulator, from the jack, so I dont think this is logical to talk about.

[SiliconWizard]

So yeah that's pretty much the same as in ANY case where you have digital signals across a cable... (the USB cable part was kind of confusing though, is it used as a JTAG cable? because otherwise, I still don't get the 2.5V. Are they implying to actually supply 2.5V so that the 3.3V regulator will just NOT regulate? Atrocious if so, but I may again not have gotten this cable thing.)

I think they mean that you should run JTAG interface at 2.5 V, so that even if there is overshoot, it won't exceed 3.3 V.

OK. Got it. Yes I think they are probably overdoing it a little here, but as you said, for liability reasons.
Could it also be possible that this extra care would come from the fact that the JTAG signals on the MAX10 ICs are on pads that are less well protected, for some design reason (/or fuck-up), than all the other IO pads?

[ataradov]

You should be fine.

BTW, those cheap USB Blaster clones work perfectly as well - https://www.ebay.com/itm/altera-Mini-Usb-Blaster-Cable-For-CSPD-FPGA-NIOS-JTAG-Altera-Programmer-NM/283453669352

[ataradov]

Could it also be possible that this extra care would come from the fact that the JTAG signals on the MAX10 ICs are on pads that are less well protected, for some design reason (/or fuck-up), than all the other IO pads?

Yeah, I'm always a bit suspicious when manufacturers put "recommendations" like this. They may know something more than they are telling us.

I have not noticed any issues, but I also have not manufactured 100K devices.

For a single development board, I would not worry about it.

[lawrence11]

It would depend on the specific board, of curse, but I'm pretty no modern FPGA board  will have 5V anything past the USB supply voltage.

What disconnection are you talking about? Are you planning on programming a custom board using terasic kit? Are you sure it actually has properly exposed JTAG for programming external parts?

disconnection, as in me physically pulling out the jtag as it is senging electricity, causing a spark/hotplug event like USB.

Its a development bord, but once im finished with the verilog, will never touch these pins again, they are not needed beyond getting the flash programmed. I dont want wasteful components no the board, I got enough small annoying things to deal with.

[SiliconWizard]

As I suggested above, I would add series resistors to the JTAG signals (I guess like 100 ohm - shouldn't be a problem for JTAG up to a couple MHz?), and ESD protection diodes.

(If you can make sure JTAG access is only done during "production" in a controlled environment, it's not mandatory, but certainly helpful if not.)

[ataradov]

There will not be sparks. Really, don't worry about it. If you really want to be safe, don't connect or disconnect the blaster while the board is powered.

[lawrence11]

Sparks is more like a metaphor, I know there wont be enough current for sparks...

My first board had this component on it,for the JTAG lines, as you can see, 4 connections for 4 lines. This was the smallest and cheapest I found.

https://www.digikey.com/product-detail/en/texas-instruments/TPD4E004DRYR/296-23618-1-ND/1913506

But its only working from 5.5 volt and over.

For my v2.0 board, I dont feel like installing such small useless things if all I must do is connect it once when unpowered, never disconnect again the header is quite a tight fit and wont accidentally disconnect.

I'll think of some programming jig later with some integrated TVS.