Lattice XO2 VCCJ voltage and external clock amplitude

[Axk]

Designing a simple breakout board for Lattice XO2-1200 (LCMXO2-1200ZE-1TG100CR1) (this particular chip because ebay has it).

Planning to program it with a chinese JTAG cable which is apparently very similar to Lattice's HW-USBN-2B (https://www.ebay.com/itm/Lattice-FPGA-CPLD-USB-Downloader-Jtag-ISP-Programmer-ispDownload-Cable-HW-USBN-2/392173727886)

Reading the Programming Cables PDF (FPGA-UG-02042-26.0) and it's clear but I'm not completely sure what VCCJ would be on the chip.
Is it VCCIO of the IO bank that has all the JTAG pins?

Another thing that I'm not sure about is what amplitude should the single ended primary external clock applied to a ACLKT pin be. Should it be VCCIO or the core VCC?

Any other gotchas you know of with trying to program an XO2 with such cables? (I've seen the pull-up resistor recommendations, so I'm adding those)

[Bassman59]

Reading the Programming Cables PDF (FPGA-UG-02042-26.0) and it's clear but I'm not completely sure what VCCJ would be on the chip.
Is it VCCIO of the IO bank that has all the JTAG pins?

Yes.

Another thing that I'm not sure about is what amplitude should the single ended primary external clock applied to a ACLKT pin be. Should it be VCCIO or the core VCC?

Always the VCCiO of the pin's bank.