Generating a 600KHz clock with 10ps Jitter

[radiolistener]

We're not debating the influence of the jitter on the ADC performance, and you're already posted 3 times about this.

sorry, I just confused you with other guy who doubted the influence of jitter on the the ADC performance

[radiolistener]

FPGA wins because everything is compact and you already have your signal inside FPGA.

unfortunately the opposite - FPGA fails.

FPGA has much more components inside and much more complicated and configurable circuit than simple and fast hardware D flip-flop. This is why FPGA has 300-650 ps jitter and 74HC IC has just 4.95 ps jitter.

[NorthGuy]

As I quoted Cyclone 4 datasheet above, FPGA has 300-650 ps jitter.

The 300/650 ps is the PLL jitter. Since you do not use PLL, this is irrelevant. FPGA has lots of things inside, and the performance depends on things you actually use. I don't know about Altera, but on Spartan-7 (and 6 too) it's a very short path from the external input clock to the output flops. It's done by design to improve IO performance. There's no specs, but I would certainly expect it to be similar to discrete ICs.

74HC series has about 4.95 ps jitter.

If you want to compare to 74HC then Spartan-7 is likely to have much better characterisics. If you look at the switching frequency, 74HC series are rated for 50 MHz or so, while Spartan-7 is rated for 800 MHz (and can produce 1.6 GHz DDR). I would expect jitter to be better too, but there's no specs. I couldn't find jitter in 74HC74 specs neither.

Of course, 12 GHz flops probably have less jitter, but one of them costs like 5 Spartan-7 FPGAs. But then there are some 7 nm FPGAs which cost more than my house and I guess they might be even better.

[radiolistener]

The 300/650 ps is the PLL jitter. Since you do not use PLL, this is irrelevant.

according to my tests, it has about 200-500 ps with no use PLL. Unfortunately I don't have equipment to measure it precisely, but I know that it is much worse than 100 ps. Other peoples have the same experience.

External 74HC gives much better jitter performance.

[radiolistener]

I don't know about Altera, but on Spartan-7 (and 6 too) it's a very short path from the external input clock to the output flops.

As I know, the minimum jitter which can be achieved on Spartan-6 is 177 ps.

it's a very short path from the external input clock to the output flops. It's done by design to improve IO performance.

don't confuse electronic delay and jitter. Electronic delay may be some nanoseconds with jitter smaller than 1 ps. The opposite is also possible - femtosecond delay with nanosecond jitter.

Electronic delay (propagation delay) doesn't equate to jitter. Don't confuse these.

[radiolistener]

Of course, 12 GHz flops probably have less jitter, but one of them costs like 5 Spartan-7 FPGAs. But then there are some 7 nm FPGAs which cost more than my house and I guess they might be even better.

I don't know about hi-end 7-nm FPGA, may be it has better performance. I don't have it and I don't know people who worked with them. But I have Cyclone 4 and it has 100 times worse jitter than 74HC. And I know other peoples who got the same result. Also I know that other people get 177 ps jitter at best case for Spartan-6. So, it looks like both Cyclone-4 and Spartan-6 have similar jitter.

There's no specs, but I would certainly expect it to be similar to discrete ICs.

It cannot have the same jitter with discrete IC, because FPGA circuit is much more complicated, it has much more elements, much more complicated crystal layout, more gates, more noise sources. So, this is not surprise that it's output has much more phase noise than plain and simple 74HC. More phase noise means higher jitter.

if you don't believe me, just hold the receiver antenna close to the FPGA chip and then to 74HC. You will hear much higher noise near FPGA chip. This noise leads to higher phase noise/jitter, no wonder.

Regarding to 74HC, there are different measurements by different peoples, some give 4.95 ps, some 5 ps, some 6 ps. Since different source give almost the same result around 5 ps, we can assume 5 ps per gate for that IC.

[NorthGuy]

But I have Cyclone 4 and it has 100 times worse jitter than 74HC. And I know other peoples who got the same result. Also I know that other people get 177 ps jitter at best case for Spartan-6. So, it looks like both Cyclone-4 and Spartan-6 have similar jitter.

FPGA is a diverse thing. It has lots of stuff inside, and everything is programmable. You cannot characterize all the designs by a single number. A crappy design will have lot more jitter than a good design. You certainly can design something with extraordinary levels of jitter. If you did that, it would be preposterous to say that FPGAs have inherently high level of jitter.

It's like if you said that PCs are slower than dedicated calculators because 100 people have tried a cloudy JavaPython calculator program on them and found that this was slower than a real calculator.

It's all in the design.

[radiolistener]

A crappy design will have lot more jitter than a good design. You certainly can design something with extraordinary levels of jitter. If you did that, it would be preposterous to say that FPGAs have inherently high level of jitter.

Yes, but the best reported jitter obtained with FPGA is about 100-200 ps. A lot of people with different design have similar results - about 150-170 ps. And datasheet specification also shows the same values - 300 - 650 ps. All results corresponds to each other and corresponds to the datasheet. And there is no way to get jitter bellow 100 ps on FPGA.

This is well known problem that FPGA output has too high jitter, which prevents to use it as a clock source for a high dynamic range ADC.

It's like if you said that PCs are slower than dedicated calculators because 100 people have tried a cloudy JavaPython calculator program on them and found that this was slower than a real calculator.

No, I just know that many peoples tried it and there is no success. All results shows that it is higher than 100 ps. And datasheet shows much higher values. So there is no sense to expect that the jitter will be less than 100 ps.

Regarding 74 series I was seen one science work with jitter measurements for some IC series. And it also show the same jitter level about 5 ps. Unfortunately cannot find it now. But found at least 4 different sources with similar results (4-6 ps).

For example:
https://www.sciencedirect.com/topics/engineering/sampling-clock

Therefore, systems that require very high dynamic range and very high analog input frequencies also require a very low jitter encode source. With care phase-locked loops (PLLs) using VCXOs can achieve less than 1 ps RMS jitter, but jitter less than 0.1 ps RMS requires a dedicated low noise crystal oscillator, as discussed in the previous chapter. It should be noted that the jitter of a typical TTL/CMOS gate to about 1–4 ps. Low voltage SiGe reduced swing ECL gate can have about 0.2 ps RMS.

https://www.diyaudio.com/forums/digital-source/24908-buffer-choice-iis-direct-4.html#post293292

Some words about typicaly jitter values of differential transmitters/receivers, logic gates and digital isolators.

ADM1485 5ps RMS
SN65LVDS050 2ps RMS
MC10124/125 0.8ps RMS
100PU124/125 0.2ps (? ? ?) RMS
74LS family 8ps RMS per gate
74HC family 6ps RMS per gate
74ACT family 3ps RMS per gate
74AC family 2ps RMS per gate
74ABT family 0.8ps RMS per gate
MC100 family 1.5 ps RMS per gate (russian equivalent is K1500)
MC10 family 0.6ps RMS per gate (russian equivalent is K500)
100 family 0.1ps(? ? ?) RMS per gate (russian military aerospace equivalent of MC10)
AD8611 1 ps RMS (I measure only 5 items, results maybe has statisticaly unreliable)
ISO150 4 ps RMS
ADUM1100BR 4 ps RMS

[Someone]

I don't think it's possible with anything.

This is possible with low phase noise oscillator and high speed logic IC.

As I mentioned above, 74LS00 has jitter about 4.95 ps.

14 GHz D-flip-flop high speed IC has jitter specification about 2 ps.
More fast logic IC has 0.2 ps jitter.

ABRACON ultra low phase noise oscillators have maximum guaranteed 75 fs rms jitter over 12kHz to 20MHz BW.

As you can see, you can get 5 ps jitter with 74 series TTL logic.
Or 0.25 ps jitter with more fast high speed IC (not TTL, but RSECL or PECL).

This is at least 60 times better than you can get on dedicated clock output of FPGA and even 130 times better than regular FPGA I/O.

Non-sense. Any datasheet reference?

You can find it in the "Cyclone IV Device Handbook":

Dedicated clock output period jitter: 300 ps

Regular I/O period jitter: 650 ps

Perhaps you have no idea what you are talking about?

FPGA specifications are worst case guaranteed cycle-cycle (period) jitter.
Everything else you are quoting are RMS figures.
The 75fs you quote is a band limited measurement.

Having measured clocks (including FPGA structures and PLLs) for these parameters I know you are just talking nonsense, come back with some RMS figures for FPGAs when they were optimised for that. FPGAs can be a low noise frequency reference but you need to know both what the actual requirements are (this thread is a mess here), and how to use FPGAs effectively.

[NorthGuy]

according to my tests, it has about 200-500 ps with no use PLL. Unfortunately I don't have equipment to measure it precisely, but I know that it is much worse than 100 ps. Other peoples have the same experience.

I can give you an idea. Attach two separate oscillators to the FPGA. Forward one out of FPGA, connect it externally to a different pin, and sample it with a clock from the other oscillator. Since the oscillators are a little bit different in the frequency, one will be slipping relative to the other. There will be a long period of '1' then a long period of '0', then '1' again etc.

If there were no jitter, the transition would be momentary - you get '1', and then you get '0'. However, because of the jitter, there will be a transitional period - where '1' and '0' are mixed. You just record the length of the transitional period Tt. And you compare it to the full cycle Tc. Then, you calculate the estimate of jitter:

J = P * Tt/Tc

where P is the clock period and J is the jitter.

For example, you have two 50 MHz clock sources. If they are 10 ppm, say one is 50.0005 MHz and other is 49.9995 MHz. So, the fast one will outpace the slow one by the whole cycle in approximately 1/(50.0005 - 49.9995) = 1 ms (if you're lucky, this may be much longer giving you better resolution). Say, you detected the period where '1' and '0' were mixed which lasted 250 samples = 5 us. Then you have:

Tc = 1 ms = 1000000000 ps
Tt = 5 us = 5000000 ps
P = 20 ns = 20000 ps

J = 20000 * 5000000 / 1000000000 = 100 ps

If the period is longer than 250 samples, the jitter is more than 100 ps. If the period is less than 250 samples, the jitter is less than 100 ps.

Then you repeat the experiment, but take the FPGA output out of the loop - you enter one oscillator as data into FPGA and sample it with the clock from the second oscillator. This way, you get jitter value without FPGA involved - J0. Then you calculate how much jitter can be attributed to the FPGA:

Jfpga = sqrt(J^2 - J0^2)

Similarly you can test your logic ICs and various frequencies.

All you need is an FPGA board with footprints for 2 different MEMS. This would seem to be a common thing, but I looked through all mine and I haven't found any.

[radiolistener]

come back with some RMS figures for FPGAs when they were optimised for that.  FPGAs can be a low noise frequency reference but you need to know both what the actual requirements are (this thread is a mess here), and how to use FPGAs effectively.

What do you mean "when they were optimized for that"?

For example I have oscillator connected to the FPGA. Let's say, I want to divide it by 2 and feed it into ADC clock. What do I need to do in order to get 10 ps RMS jitter on the output? FPGA is EP4CE22E22C8

[NorthGuy]

Let's say, I want to divide it by 2 and feed it into ADC clock. What do I need to do in order to get 10 ps RMS jitter on the output? FPGA is EP4CE22E22C8

Read the datasheet, especially the part on clocking. Find out how to route an external clock to the flip-flop closest to the output pad. Do this. Then write some logic clocked with the same clock which feeds a fixed pattern to the above flop, such as "10" if you want to divide by 2, or "111000" if you want to divide by 6 etc. Or, you can use a SERDES if your FPGA has them - then you don't need the logic as SERDES will feed the pattern for you. Then measure the jitter.

Edit: This would give you the best jitter, but nobody knows what it is

[radiolistener]

If there were no jitter, the transition would be momentary - you get '1', and then you get '0'. However, because of the jitter, there will be a transitional period - where '1' and '0' are mixed. You just record the length of the transitional period Tt. And you compare it to the full cycle Tc. Then, you calculate the estimate of jitter:

J = P * Tt/Tc

where P is the clock period and J is the jitter.

That is interesting, I have board with two places for oscillators, but unfortunately don't have two equal oscillators. Does this approach really allows to measure jitter? Could you please suggest me some article about that, just want to understand how it works 

[radiolistener]

Find out how to route an external clock to the flip-flop closest to the output pad. Do this.

Do you mean something like useioff synthesis attribute in verilog?

[NorthGuy]

Find out how to route an external clock to the flip-flop closest to the output pad. Do this.

Do you mean something like useioff synthesis attribute in verilog?

I don't know, I use VHDL, but this sounds like a correct word to select IO flop. It is also important to use the best clock buffer. Say, in Spartan-6 it's called BUFIO2. In Spartan-7 it's called BUFIO.

That is interesting, I have board with two places for oscillators, but unfortunately don't have two equal oscillators. Does this approach really allows to measure jitter? Could you please suggest me some article about that, just want to understand how it works 

More like rough estimate. I don't have an article. You just select the period when the clock edges are very close to each other, close enough so that the jitter is able reverse them (this way you get '0' in the middle of '1's or vise versa). As soon as the clock edges move further apart, the jitter cannot harm the sampling (this way you get all '1' or all '0').

They don't have to be the same. It's enough for one to be a divide for another, say 10 MHz and 50 MHz (you then sample with the slower clock), but they must be accurate enough to stick close together long enough to make the measurements.

[BrianHG]

come back with some RMS figures for FPGAs when they were optimised for that.  FPGAs can be a low noise frequency reference but you need to know both what the actual requirements are (this thread is a mess here), and how to use FPGAs effectively.

What do you mean "when they were optimized for that"?

For example I have oscillator connected to the FPGA. Let's say, I want to divide it by 2 and feed it into ADC clock. What do I need to do in order to get 10 ps RMS jitter on the output? FPGA is EP4CE22E22C8

You should be getting better than 43ps jitter as long as you are using a dedicated PLL, have proper low noise power supplies with proper analog ground planes and capping for the PLL, plus, you must have that IO's assignment setting set to 'Fast Output Registers' enabled, with NO asynchronous clocking/resets/presets for that output D flipflop.  With that IO's neighboring twin producing a a negative mirror image of the signal, again with 'Fast Output Registers' set for it, you should hit somewhere below 30ps jitter except under poor power supply conditions, or if you diverted from my above specifications.  Also, the PLL clocking that flipflop should be at a high frequency.  The assignment settings must be done separate and are not specified within verilog source code.

[ejeffrey]

I don't think it's possible with anything.

However, there's no reason why 74 series ICs should be any different than FPGAs - they're built on the same technology and there's no reason to believe they would have dramatically different characteristics.

You absolutely can do 10 ps, it isn't even terribly good.  High quality clock distributors have under 100 fs of added jitter (although these use ECL not CMOS).  Single digit picoseconds is no problem with standard CMOS.

 There are several reasons FPGAs are worse althoughh how bad depends very strongly on how you use it.  For instance the onboard PLLs are not great.  The clock distribution networks are ok, bit still go through multiple gates.  Best is to use a fast output register clocked by a dedicated clock coming in from the same bank as the IO.  Even so it probably has more gates than a single flip flop.  In addition by being inside an fpga you are subject to the temperature and supply voltage variations from the FPGA which affect trigger threshold and delay.  If your fpga isn't doing anything else that may not be a problem but then why use an FPGA at all?  If you are doing the clock generation on the same FPGA that is collecting the ADC data and processing it then you likely will suffer from these sources of added jitter.

Although you probably cannot achieve 10 ps, you can try to do the best you can. If you use more components, more PCB traces, more legs, more vias etc., you will get more jitter because each of these elements can only add jitter, but cannot remove it.

But you can subtract jitter by retuning the signal with a dedicated flip-flop that has its own low jitter clock that doesn't travel through the FPGA.

Thus the key is to use less of everything - straight PCB traces, good bypassing, less components, less things that can add jitter. In this respect, FPGA wins because everything is compact and you already have your signal inside FPGA.

All of that is correct except the last sentence which is inverted.

[nctnico]

Hi,
I have used AD9517-3 in a ZYNQ project before, Now I have a new project, which I need to sample a low speed ADC with 600KHz sample clock, but the problem is that, my customer needs a maximum 10ps jitter sample clock. I told them I will use AD9517 with the fs jitter, But I will divide the generated clock inside the FPGA to achieve the low speed clock with low jitter. But they told me they had a problem with this Technic and spartan 6 before, the Flip-flops inside the FPGA and in the last stage will determine the over all jitter, and they would add so much jitter (in the range of 100-200ps) to the generated clock. so do we have a way of creating a low speed clock with low jitter?

Your customer is not informed properly. If you clock the FPGA from the AD9517 the jitter of the output signal will have slightly worse jitter but not much. Certainly not 100ps. I think your customer is mistaken by the internal DPLLs in the Xilinx FPGAs. These do introduce tens to hundreds ps of jitter but as long as you don't use these to divide the clock signal you should be OK.

[ali_asadzadeh]

The ADC is LTC2378, I need to do another design though! it's acceptable to use 150ps jitter with a 200Khz sample clock, so I think I should the external clock chip for this design too.

[nctnico]

Don't make your design more complicated than it has to be. Just be sure to read the specifications. If your ADC doesn't need a 50% duty cycle square wave then it is even easier to make a divided clock inside an FPGA without using the internal DPLLs. You can clock everything from a standard oscillator module (but check the jitter specs to make sure). Likely you can use standard 74HC / HCT CMOS logic chips to make the divider if you are only after a divider. Chances are that the internal PLL of a standard microcontroller is up to the task as well so you could use a timer output to generate the clock. I have done this in several designs.

[iMo]

Non-sense. Any datasheet reference?

You can find it in the "Cyclone IV Device Handbook":

Dedicated clock output period jitter: 300 ps

Regular I/O period jitter: 650 ps

I ran through the document searching for "jitter". I have not find any reference to something related to the jitter of the logic itself. Everything there is related to PLLs, or various on-chip transceivers..

[dietert1]

This is an evaluation kit schematic from LT/AD using one of those ADCs. Can you find the sync flip-flop?

https://www.analog.com/media/en/technical-documentation/eval-board-schematic/710-dc2289a_rev01_pca_schematic.pdf

The ADC datasheet says aperture jitter is 4 ps typical. No need to be much better than that.

Regards, Dieter

[Marco]

Just need to use a clock which is a multiple of 600 kHz instead of the 100 MHz.