MIPI RX low frequency

[worldmasters]

Hello. I have a GW2AR-LV18EQ144C8/I7 chip. I need to set up the camera operation. I use a standard IP Core from the manufacturer GOWIN.

I wrote the simplest code. In it, I connected one MIPI_RX_Advanced module in the Top module.

Code: [Select]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;


entity top is
port ( 
    clk: in std_logic:= '0';    --генератор входного клока на 50мгц
 
HS_CLK_P_io: inout std_logic := '0';
HS_CLK_N_io: inout std_logic := '0';

HS_DATA1_P_io: inout std_logic := '0';
HS_DATA1_N_io: inout std_logic := '0';

HS_DATA0_P_io: inout std_logic := '0';
HS_DATA0_N_io: inout std_logic := '0';

out_d:out std_logic_vector(15 downto 0)
);
end top;


architecture structural of top is

signal clk_byte_out_o: std_logic;
signal data_out1_o: std_logic_vector(7 downto 0);
signal data_out0_o: std_logic_vector(7 downto 0);
signal ready_o: std_logic;

component MIPI_RX_Advance_Top
port (
reset_n: in std_logic;
HS_CLK_P: inout std_logic;
HS_CLK_N: inout std_logic;
clk_byte_out: out std_logic;
HS_DATA1_P: inout std_logic;
HS_DATA1_N: inout std_logic;
data_out1: out std_logic_vector(7 downto 0);
HS_DATA0_P: inout std_logic;
HS_DATA0_N: inout std_logic;
data_out0: out std_logic_vector(7 downto 0);
hs_en: in std_logic;
clk_term_en: in std_logic;
data_term_en: in std_logic;
ready: out std_logic
);
end component;
 
begin

your_instance_name: MIPI_RX_Advance_Top
port map (
reset_n => '1',
HS_CLK_P => HS_CLK_P_io,
HS_CLK_N => HS_CLK_N_io,
clk_byte_out => clk_byte_out_o,
HS_DATA1_P => HS_DATA1_P_io,
HS_DATA1_N => HS_DATA1_N_io,
data_out1 => data_out1_o,
HS_DATA0_P => HS_DATA0_P_io,
HS_DATA0_N => HS_DATA0_N_io,
data_out0 => data_out0_o,
hs_en => '1',
clk_term_en => '1',
data_term_en => '1',
ready => ready_o
);

lop: process(clk_byte_out_o, data_out1_o, data_out0_o)
begin

if rising_edge(clk_byte_out_o) then
out_d <= data_out1_o & data_out0_o;
end if;
end process lop;


end architecture;

I put together a project and this is what I saw on the time chart:
 

The documents indicate that this module can operate at a frequency of up to 1200Mb s.

Everything is connected on the LVDS line.
Please tell me what I did wrong and why I can't get the stated frequencies?

The project is in the application. Thanks

[mon2]

Hi. Still very much in the learning stages of this FPGA; its toolchain and specifically MIPI but for DSI use but have the following comments:

1) Yes, you have enabled the PLL to accept your reference input clock and dialing it up to your target 100Mhz (with some deviation) using the PLL registers. I think you are using a 27 Mhz clock like found on the assorted kits on the Aliexpress stores? We have seen the same target clock for the CPU.

2) Respectively, you need to enable the feature of the MIPI RX IP to make use of an external clock. Then proceed to expand the PLL to dial up a higher clock for the use of this MIPI CSI interface. No idea as to which clock you really want but you can review their documentation and also inspect the actual clock using their RAO tool which is really cool and helpful. It helped us to debug a recent MIPI DSI project rather quickly.

3) On the note on of the offshore Gowin based tools - one of them does make use of a CMOS sensor which I believe is MIPI based. Locate this on Aliexpress and then on github so you can study how they enable the use of the camera. I recall running their demo which captures live video and outputs to a local HDMI sink. Cool demo and very inexpensive tools to learn about these devices. Personally starting to really like the FPGA world since it is so flexible. Just the documentation and some of the broken IPs need factory help to improve.

See attached.