A question for experience designers. Is it common or useful to mix verilog and system-verilog files (RTL and testbenches) in the same project?
Also, is it common to distinguish between verilog and system verilog files by the extension? E.g. .v and .sv.
Very common. Your HDL tool might support Verilog syntax only (or more likely the synthesize-able subset of the Verilog language, as defined by the vendor).
Or your vendor tool might support SystemVerilog (or again a synthesize-able subset of it) language input as well.
For your testbench, if your simulator supports SystemVerilog, then your testbench might be written in that dialect, and it references your design in Verilog).
The vendor synthesis tools will never see the testbench code, so they can be written in whatever dialects of Verilog your simulator supports.
Heck you could even write your testbench in VHDL if your simulator supports mixed language input on files.
For most tools it is general practice (and may be required, depends on the tool) for Verilog files to be .v extension and SystemVerilog files to be a .sv extension.