Author Topic: Mixing verilog and system verilog?  (Read 2400 times)

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Online zaptaTopic starter

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Mixing verilog and system verilog?
« on: December 17, 2024, 08:40:31 pm »
A question for experience designers. Is it common or useful to mix verilog and system-verilog files (RTL and testbenches) in the same project? 

Also, is it common to distinguish between verilog and system verilog files by the extension?  E.g. .v and .sv.
 

Offline AK6DN

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Re: Mixing verilog and system verilog?
« Reply #1 on: December 18, 2024, 06:37:20 am »
A question for experience designers. Is it common or useful to mix verilog and system-verilog files (RTL and testbenches) in the same project? 

Also, is it common to distinguish between verilog and system verilog files by the extension?  E.g. .v and .sv.

Very common. Your HDL tool might support Verilog syntax only (or more likely the synthesize-able subset of the Verilog language, as defined by the vendor).
Or your vendor tool might support SystemVerilog (or again a synthesize-able subset of it) language input as well.

For your testbench, if your simulator supports SystemVerilog, then your testbench might be written in that dialect, and it references your design in Verilog).
The vendor synthesis tools will never see the testbench code, so they can be written in whatever dialects of Verilog your simulator supports.
Heck you could even write your testbench in VHDL if your simulator supports mixed language input on files.

For most tools it is general practice (and may be required, depends on the tool) for Verilog files to be .v extension and SystemVerilog files to be a .sv extension.
« Last Edit: December 18, 2024, 06:38:54 am by AK6DN »
 

Offline Berni

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Re: Mixing verilog and system verilog?
« Reply #2 on: December 18, 2024, 06:57:02 am »
You can even mix VHDL, Verilog and SystemVerilog in the same project for most cases.

But yeah as usual in the FPGA world, the details are very tool specific. Every vendor does things slightly differently and might support a slightly different list of features as actually being synthesizeable.
 

Offline xvr

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Re: Mixing verilog and system verilog?
« Reply #3 on: December 18, 2024, 01:30:35 pm »
BTW, from 2009 Verilog and SystemVerilog are officially the same language. Last Verilog standard IEEE Std 1364-2005 was superseded by IEEE Std 1800-2009 (which is the SystemVerilog standard)
 

Offline AK6DN

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Re: Mixing verilog and system verilog?
« Reply #4 on: December 18, 2024, 10:11:48 pm »
BTW, from 2009 Verilog and SystemVerilog are officially the same language. Last Verilog standard IEEE Std 1364-2005 was superseded by IEEE Std 1800-2009 (which is the SystemVerilog standard)

Which helps now if you are using current FPGA/CPLD design software, but if you are using legacy 90s/00s software as I do there is still Verilog vs SystemVerilog to deal with.
 

Offline asmi

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Re: Mixing verilog and system verilog?
« Reply #5 on: December 19, 2024, 03:52:13 pm »
Nowadays I only use Verilog to create a wrapper for Vivado IPI components because it still doesn't support SystemVerilog (which is a shame really). SystemVerilog is better in every way you can think of, so I see no reason not to use it.


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