My first FPGA (MAX10) design : some questions about clock and other aspects

[pantarei]

Hi all,
this is my first post here, very happy and excited to be part of this wonderfuf community!
Finally I'm doing my first FPGA design (after tons with simpler CPLDs)
I'm targeting a MAX10 FPGA (10M08SCE144C8G is the exact part name).The design will be a kind of replacement installed on an old computer (mostly made with TTL logics).I have read the Intel® MAX® 10 guidelines and  I want to feed the FPGA with a 6MHz clock signal coming from the old TTL hosting hardware.Should I simply connect this signal to one of the clock input of the MAX10 FPGA (for example pin 27 CLK0p like I did it in my schematics which I attach) or connect the signal to all 8 clock inputs CLK[3..0][p,n] so that they can drive all GCLK networks?
Other doubts concern the connection of the Configuration/JTAG Pins (CONFIG_SEL, CONFIG_DONE, JTAGEN, etc), I followed the guidelines but perhaps I missed something.I attach the schematics of the design hoping someone will shed light on this.Thanks in advance!
 

[pcprogrammer]

Welcome to the forum.

I'm not familiar with the MAX10, but for what I have seen with other FPGA's there is no need to connect your clock to more than one of the clock inputs. The routing onto the GCLK networks is done internally and depending on the design the necessary number of lines will be used.

The external clock inputs are to be used when different clock frequencies need to be inputted to the FPGA. Like for instance a clock synthesizer IC can be used to make multiple adjustable clocks that all need to go into the FPGA.

The other connections will be fine if you followed the datasheet.

One question for you though. You mention it to be a replacement for something in an old computer and TTL logic, but did you take into account that the FPGA IO is 3.3V and most likely not 5V tolerant, so level conversion might be needed.

[Gleeson]

Yes, be sure to pay attention to the 5V vs. 3.3V level shifting need.

[Gleeson]

One other thing.  It looks like you're embarking on your own custom board design.  Have you considered starting with an evaluation board to "get your feet wet"?  Here's one for the MAX10 from Terasic for $50, pretty hard to beat that.

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=708#contents

[pantarei]

Welcome to the forum.

Thanks!

I'm not familiar with the MAX10, but for what I have seen with other FPGA's there is no need to connect your clock to more than one of the clock inputs. The routing onto the GCLK networks is done internally and depending on the design the necessary number of lines will be used.

Looking at clock guidelines I thought each single ended clock CLK[3..0][p,n] pins must be connected to all  GCLK networks.But looking attached pictures the GCLK networks are connected each other.

 

The other connections will be fine if you followed the datasheet.

I only left the CONFIG_SEL unconnected.

One question for you though. You mention it to be a replacement for something in an old computer and TTL logic, but did you take into account that the FPGA IO is 3.3V and most likely not 5V tolerant, so level conversion might be needed.

Yes, I used proper ICs for voltage level translation (picture attached), they are on another sheet of schematics.

[pantarei]

Yes, be sure to pay attention to the 5V vs. 3.3V level shifting need.

Yes, I used proper ICs for level shifting.

[pantarei]

One other thing. It looks like you're embarking on your own custom board design.  Have you considered starting with an evaluation board to "get your feet wet"?  Here's one for the MAX10 from Terasic for $50, pretty hard to beat that.

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=708#contents

Yes, I've considered this option but my design has 80 I/O while it seems this evaluation board has less I/O on the headers.

[BrianHG]

This board: https://www.mouser.com/ProductDetail/Altera/DK-DEV-10M50-A?qs=bKenfurwlslqr8ev6O9%2FIg%3D%3D

Has over 100 2.5v IOs on it's HSMC CONNECTOR J2.

You also get DDR3, USB, Dual Ethernet, HDMI and a bunch of other goodies.


Also see if you can get a used Arrow DECA Max10 dev board.  76 3.3v IOs on normal dual inline connectors.
Same peripherals as above plus a 16bit stereo audio codec with line in, headphone out.