My first FPGA code

[rstofer]

If the test for equality across the data is supposed to be a clocked process (as shown above) then it can be tidied up a bit:

Code: [Select]

`timescale 1ns / 1ps
module Verilog01(
    input wire test1,
    input wire test2,
    input wire test3,
    input wire test4,
    output reg out1,
    output reg out2,
    input wire clk,
    input wire reset_n
    );
    always @ (posedge clk)
    begin
        if (reset_n == 0)
            begin
                out1 <= 1'b0;
                out2 <= 1'b0;
            end
        else
            begin
                if (test1 == test2)
                    out1 <= 1'b1;
                else
                    out1 <= 1'b0;
                if (test3 == test4)
                    out2 <= 1'b1;
                else
                    out2 <= 1'b0;
            end;
    end;               
endmodule

Furthermore, the hardware looks right, see attached.  No attempt was made to use the actual signals for the project.

[rstofer]

So, what could be a solution for this type of cross domain issue?

This is well described in the documentation.  Usually, there is a two clock delay by running everything through a string of 2 flops clocked by the receiving domain.  RTFM, this is one of the steps to priesthood.
For what I see of this project, and I clearly don't understand what is going on, I can't see why everything doesn't run off of one clock.  I have entire systems, IO devices and CPU, and they all run off of one clock.  Divided down, here and there, but one master clock.  If I wanted to, I could use the DCM (Digital Clock Manager {Spartan 3}) to clean up the timing.  This was old school, it has been upgraded to something else (probably some form of PLL) but I haven't kept track.

Have you made a state diagram?  Maybe just a transition table?  It's hard to see what you are doing - at least for me, I know just about nothing about Verilog.

[hamster_nz]

So, what could be a solution for this type of cross domain issue?

Mainly care and skill, using things like dual clock FIFOs, careful two-way handshaking, Grey counters and more.

Nothing specifically "Verilog". Verilog is just the language you implement things in.

[asmi]

As far as I can tell, your problem seems to be that you've bitten more than you can chew, which is why you seem to be permanently confused. Get yourself a good book, or follow some tutorial which would introduce features one-by-one and explain them immediately, and do not throw yourself into a wall of code that does God knows what. For books I would recommend "Digital Design and Computer Architecture: ARM Edition" (bonus points to this book for showing VHDL and SystemVerilog code side-by-side which helps to demonstrate just how much of a crap VHDL is), If you prefer video tutorials, I would highly recommend Russell Merrick's Nandland Go board and a set of excellent video tutorials for it: https://www.nandland.com/goboard/introduction.html This guy is a professional FPGA designer, so he knows what he is talking about, and again, he explains and introduces things slowly so that everyone can keep the pace.
What I don't recommend is you do it the way you're doing know - get some random code from the Internet that does who knows what, and do some random changes in it hoping that you will understand what's going on. The reality is your won't. Here is something that you probably don't expect to hear - reading (and understanding) someone else's code is hard, in many cases it's much easier to write your own code from scratch then to figure out how someone else's code works. So start from simple things - what is wire, what is LUT, what is flip-flop, how to use all of that in HDL, and slowly build up to more complicated concepts (UART, SPI, I2C, etc.). The most important thing here is to make sure you completely understand whatever feature or code you're studying before you move on to something else. Basic concepts of HW design should be crystal-clear to you before you have any chance of understanding anything more complex. It's like an alphabet - you can't use the language until you at least learn it, or like a decimal numbers for math - you can't hope to understand anything in math until you learn how to use numbers.

[lawrence11]

I already past the level of these uart things.

I'm here now, @ the clock crossing domain lesson.

No time to waste to go back to beginner stuff, this is way better like I'm doing it now, asking the forum teachers what went wrong in my homework.

Like you should do, @ school.

[rstofer]

That "Digital Design ..." book is excellent!  I don't agree about VHDL being crap but that's not the point.  It is a very good book.  Yes, VHDL is wordy.

I just ran across NandLand today and I have started the tutorials.  They are very well done!

You are spot on about code from the Internet and the difficulty in understanding random code.  I have enough trouble reading my own code.  One thing:  Don't write the most clever code on the planet, it will jump up and bite you in the ass when you come back to it a week later.

[lawrence11]

This is not code from the internet, this is my code, and its the easiest frikkin example to understand.

[hamster_nz]

I already past the level of these uart things.

I'm here now, @ the clock crossing domain lesson.

No time to waste to go back to beginner stuff, this is way better like I'm doing it now, asking the forum teachers what went wrong in my homework.

Like you should do, @ school.

Trying not to be rude... I feel you are still way below the level of understanding required to implement a UART from scratch.

You should take the advice and get a good book (or even a PDF). There is nothing wrong with learning from a book.

[lawrence11]

http://hdlexpress.com/Verilog/VT.html

I have a uart example right here, with a state machine, and tb.

first link.

[lawrence11]

NO, I disagree!

[rstofer]

I have a uart example right here, with a state machine, and tb.

Yes, but you didn't write it.  There's a ton of code at OpenCores.org that I can grab - but I didn't write it.  And I won't ever really understand how it works because I didn't write it.  I can read it until I'm blue in the face but I still won't understand it if I didn't write it.  From scratch, no crib sheets.

The same goes for tutorials.  I don't learn as much just watching the video as I do when I type the code and run it.  Simply doing a copy-and-paste doesn't count.  Actually typing the code gives the best results - for me.

[lawrence11]

Yeah it counts, I understand his code. Once I can simulate I can mess around.

Its mine now.

BUT, he never goes with a hard example, with multi module. how to link many module to 1 test bench. Show me a multi module, 3 module=37 module.

1 module=? I am still confused. Clock domain I am still confused.

He just says, you gotta work like this.... presents graphs, gives an easy example.

So... Are we getting any close to a solution? Is it a double buffering type scenario?

[lawrence11]

Hey why dont canadians give good answer to fellow canadians?

You guys are just trolling me.

Dont mind me, I just wanna invent the stuff I was destined to invent.

Nobody is gonna hire me, dont worry...

[lawrence11]

Ok I get it hamster, This is the scenario of double buffering, and you said the time is not accounted for.

Are you aying such a buffer would be 1 clock late and to pass from 1 domain to another I need an extra clock thus 2 clocks, and in this particular example the error is evident?

End result, I see a sim that has perfectly enough time for the electrons to do its job, but its bugged.

What is the recipe to solve this? I must pass the value to an intermediate register?

Can we stop being gatekeepers now. I watched the videos, I have it in front of me, I dont get it.

[hamster_nz]

Ok I get it hamster, This is the scenario of double buffering, and you said the time is not accounted for.

Are you aying such a buffer would be 1 clock late and to pass from 1 domain to another I need an extra clock thus 2 clocks, and in this particular example the error is evident?

End result, I see a sim that has perfectly enough time for the electrons to do its job, but its bugged.

What is the recipe to solve this? I must pass the value to an intermediate register?

Can we stop being gatekeepers now. I watched the videos, I have it in front of me, I dont get it.

The data bits are being received when SPI_CLK changes.

And do you agree that the design is testing the value of 'important byte' after it is received - the data assembled from bits that receive every time SPI_CLK ticks, and then the received value used for the comparison when the clock next ticks.

What happens when the source stops ticking the SPI_CLK signal, because it has sent all the data?

Can you see that there is the problem?

Maybe an example of what is going on - where the send send 'A', 'B', 'C' & 'D' a minute apart, then waits 56 minutes before send 'E' & 'F':

Code: [Select]

Time  Receiving   Testing - is it 'D'?
0:00        A           -
0:01        B           A
0:02        C           B
0:03        D           C

... Sender pauses for an 56 minutes, before sending 'E'

1:00        E           D <<< Yes it was D, but that was 56 minutes ago!
1:01        F           E

Do you agree there is a problem, or have I lost you?

[emece67]

.

[lawrence11]

Hamster, yeah you have lost me.

@ Emece67, These kind of gatekeeping posts have their use, thank you.

But I disagree @ your solution, wich is nowhere to be found.

I just send this example on reddit and everybody is wrong.

https://www.reddit.com/r/FPGA/comments/e1bk0c/please_help_me_understand_verilog_and_a_workflow/

Everybody who gives long answers cant find the problem. I think they just dont know verilog enough.

You can see here, that people are upvoting wrong answers, and that most people are bad @ Verilog.

None of you are smarter than Hamster, so far.

[lawrence11]

Ok I'll be honest here.

I think that about 50% of people who studied Verilog, claim to know Verilog on their resume. Dont really know Verilog and just struggle their whole lives.

Dont know the answer and couldnt  find the cause/fix if I gave them this file.

[emece67]

.

[lawrence11]

Ok I'm gonna have to digest this. I read about this honestly, but its like chinese almost, I need to really think about it.

Thanks alot. I'll have to go and relay this message, in a more understandable format to those people on reddit.

Reddit has been going downhill for a longtime now, its as if the xbox crowd moved to /fpga.

[hamster_nz]

For what it's worth, that junky testbench was written assuming that it really was a SPI connection (with SPI_CSn, SPI_CLK and SPI_MOSI signals) that were being driven by an external device (a microcontroller, a Raspberry Pi, whatever...).  If that is the case, the SPI_CLK doesn't have to be continually driven, hence why the whole SPI transaction was in it's own initial block. It it was driven con

At some point a true, independent clock for the FPGA will be needed, along with a proper reset signal (rather than using a SPI signal) , which both deserve their own blocks 'initial' or 'always' blocks in the test bench.

For @lawrence11 benefit, attached is the image of a SPI transaction from https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html with data sampled on the falling edge and shifted on the rising edge.

PS. Oh how I wish SPI didn't have the whole different Clock Polarity and Clock Phase thing... I am yet to get to grips with it, get it wrong 75% of the time.

[rstofer]

Using the SPI clock in the FPGA clock domain is problematic.  The CSn, Clk and MOSI (assuming the FPGA is the slave) need to be synchronized with the FPGA clock domain.  I will assume the FPGA clock is faster than the SPI clock but it doesn't have to be if FIFOs are used.

Since my FPGA boards typically run at 50 or 100 MHz, I don't see the SPI clock as being faster so what we have are signals from a slow domain transitioning into a fast domain.

Here's how it is done:

https://www.nandland.com/articles/crossing-clock-domains-in-an-fpga.html

Yes, it's in VHDL but it translates easily.  I would make it a 1 signal in/out module and instantiate it everywhere I had signals coming from outside the FPGA into the FPGA.  Or make it generic in terms of width but that's above my pay grade.  Note that the code also deals with pulses.

Debouncing manual switches is an entirely separate issue.

This is one of those cases where the unsynchronized signals will look fine in simulation because the simulator synchronizes everything but in the real world it fails badly.

[rstofer]

If this code ever starts to look like a FSM (and it probably will), it would be nice to start a timer on the falling edge of CSn and test it for timeout in every state.  The transfer is aborted if the timer times out and the code then branches to a state where it waits for CSn to go high before returning to some initial state where it is waiting for CSn to go low.  This state where the code waits for CSn to go high will exist anyway, nothing is added. I guess an error flag could be set but so far, this project doesn't have a register style interface.  It doesn't look like a controllable peripheral.  I'm not saying it has to have a register interface but it's a pretty common idea.

[Bassman59]

I ended up choosing Verilog because A) VHDL reminds me of COBOL (so elegance is certainly in the eye of the beholder here), B) most of the open source tooling I found is based around Verilog and SystemVerilog, and C) the default synthesis language in Vivado HLS is Verilog.

In the course of my career, I have had to use both languages ... and the choice of language was made by my employers. That said, now I work for a VHDL house, so by default it is my preference. (Actually, it's always been my preference.)

I'm pretty sure that my experience is common.

[Bassman59]

I initialised it to 1 in the initial block, clearly it should get assigned back to 0 on the posedge no?.

So "ticking in an always block" is not the same as assigning to 1 outside an always block, even tho it creates a posedge?

 

Here is the odd thing about initial and always blocks.

They run in parallel.

I learned Verilog long ago, long enough ago to have used the SILOS III simulator, and to have found a bug in it, and I called them up on the phone and spoke to one of the developers who said, "Yep, that's a bug, look for a fix shortly ..." and one of the things which was pointed out was that the initial block is not an initializer block! That is, it was never intended to be something where you stuff all of your signal resets and initializers. But somehow synthesis semantics have made it so.

Basically the differences between the two blocks are:
a) The initial block cannot have a sensitivity list, which means that
b) it runs only at the start of time and when it suspends it's done. It never goes back up to the top of the block and start executing again, and it needs to have waits and delays to advance time.
c) An always block has a sensitivity list, which means that it wakes up whenever there is a transaction on the signals in its sensitivity list. (If an always block doesn't have a sensitivity list, you need to make sure that there are waits or delays to advance time. It's almost like an initial block in that sense but execution jumps back to the start of the block when it reaches the end.)

Now if you assign a wire to 1'b1 outside of an always (or initial) block, congratulations, you have made a constant. If you assign to the same signal inside a block and outside, well, you can't do that -- as noted before, signals assigned inside a block (either initial or always!) must be of reg type; signals assigned outside the block must be wires.

To be honest, this sort of silliness (and the whole idea of blocking and non-blocking assignments in a block) is why I prefer VHDL over Verilog, where the semantics of the language are clear.