NCO to generate square wave

[Evan.Cornell]

I need to produce N (probably less than 16) number of square waves, fixed 50% duty cycle with frequency of 1MHz, but each independently variable in frequency with steps of no more than 100Hz, within ~50kHz on either side of 1MHz.

Are N channels of numerically controlled oscillator (NCO) blocks within FPGA a plausible method to do this?

I found a VHDL snippet here https://gist.github.com/RickKimball/45d0753a900f92d5fdd836746062588c that seems to be rather compact.

[langwadt]

all you need is an adder per output, the MSB is you squarewave

but you will have jitter of +/- a clockcycle

[oPossum]

Skyworks (formerly Silicon Labs) has several clock generator chips with multiple outputs. Many with 8, a few with 12.

https://www.skyworksinc.com/en/Products/Timing-Clock-Generators

[SiliconWizard]

A resolution of 100 Hz? Wow. The difference between the period of a 1 MHz signal and 1 MHz + 100 Hz is just about 100 ps.
You can get an average frequency with that resolution using the technique mentioned above without requiring an actual resolution of 100 ps (which would require a base clock of 10 Ghz!!), but then you'll get inevitable jitter. What is the acceptable jitter here?

[BrianHG]

If you want jitterless, then you will end up having to use long-division low frequency phase comparator (like 100hz) PLLs designed for this purpose.  Though, you would need 16 of them and an MCU to control all or for the strict phase comparator with VCO, you would need an FPGA to generate all 16 reference 100hz output signals + the high frequency 1MHz signals.

Using a DDR trick with CycloneIV/MAX10, I have generated 1ns step accurate (equivalent to a 1GHz base clock) outputs running the core clock at 500MHz.  Since you need 100ps, as SiliconWizard said, you would need an FPGA with a 10gbps transmitter to pull this off with 0 added jitter where as my trick would generate an additive corrective 1ns jitter once every 1-9 output toggles unless you tune the output right on any integer 1000hz offset of 1MHz.

[NorthGuy]

With delay elements and/or phase shift, it should be possible to achieve 100 ps resolution, may be even better.

[Someone]

Are N channels of numerically controlled oscillator (NCO) blocks within FPGA a plausible method to do this?

As above, the answer is yes if you either:
don't care about jitter
or
do some in depth/complex use of the hard resources

[Evan.Cornell]

Thanks all for the replies. I don't think jitter is a huge concern for the application.. the purpose of the tunable square wave frequencies is to be able excite a transducer right at its resonant point, which will vary based on individual transducer characteristics. I think as long as the average frequency is tunable, cycle-to-cycle jitter shouldn't be too detrimental to the application.

I have definitely seen the SiLabs / Skyworks line of clock generators, but availability is awful right now, so was exploring the FPGA/NCO option, hopefully with one of the various sub-$10 parts from Lattice that seem to be relatively easily available these days.

[ejeffrey]

Is it important to not unintentionally excite a different transducer?  A simple clocked square wave generator will have quite some spurs.  If that is a problem you will probably need to do something better.

Do you want to do this with just the FPGA or can you use external components?

The bog standard way to do this is a fractional N PLL.  You can get 1 Hz resolution without using an excessively low phase comparison frequency.

Another approach is to use a NCO + DAC to generate a sine wave, low pass filter it and then use a high speed comparator to make the square wave.  Even a low resolution DIY resistive ladder DAC will help.

Depending on your transducer characteristics you could forgo the fpga entirely and make oscillator circuits using the transducer itself as the frequency selecting element.

Each take substantial extra components for 16 channels but will produce more spectrally clean output if that is important.

[SiliconWizard]

Thanks all for the replies. I don't think jitter is a huge concern for the application.. the purpose of the tunable square wave frequencies is to be able excite a transducer right at its resonant point, which will vary based on individual transducer characteristics. I think as long as the average frequency is tunable, cycle-to-cycle jitter shouldn't be too detrimental to the application.

Then definitely try the approach with a phase accumulator. The higher the base clock, the lower the jitter you'll get. A 100 MHz base clock sounds reasonable here for what you want to achieve and should be no problem even on a modest FPGA. It's a couple hours work, so I'd definitely prototype this first and see if it fits your requirements.

[Evan.Cornell]

Is it important to not unintentionally excite a different transducer?  A simple clocked square wave generator will have quite some spurs.  If that is a problem you will probably need to do something better.

I don't think this is an issue for my application.

Depending on your transducer characteristics you could forgo the fpga entirely and make oscillator circuits using the transducer itself as the frequency selecting element.

Any implementation examples here? The idea is to adjust the frequency to hit each transducer's specific resonant point, but if there's an analog way to do this without manual adjustment, that would be most desirable.

[SiliconWizard]

Are those ultrasound piezo transducers?

[Evan.Cornell]

Are those ultrasound piezo transducers?

Yes.

[hamster_nz]

On Xilinx 6 or 7 series the SelectIO SERDES is good to about 1Gb/s.

500 bits on, 500 bits off gives 1.000MHz
499 bits on, 500 bits off gives 1.001MHz  (not perfectly square duty cycle, but near enough)
499 bits on, 499 bits off gives 1.002MHz

That is with minimal jitter.

499 bits on, 500 bits off, followed with nine blocks of 500 bits on, 500 bits off = 10 pulses over 9,999 cycles = 1.000100 MHz with some jitter

If that meets your needs, then it is perfectly achievable with a little bit of actual design work.

[Evan.Cornell]

Do any of the regular pins on spartan 7 work in that 1Gbps mode?

[hamster_nz]

> Do any of the regular pins on spartan 7 work in that 1Gbps mode?

Yes. Different grades have different speeds.

See table 15 (on page 15) of https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf for specs.

[BrianHG]

Dont know about spartan, but with altera, I do know that you can get the DDR DQ pins to do the 1GHz unbalanced, IE 2.5v or 3.3v outputs.  Meaning a 1ns jitter with with a NCO.  (Note that I have 2 projects online here at EEVblog which do run CycloneIV and Max10 at this 1GHz with read/write data, so I know it can be done.  I got the bottom end slowest CycloneIV to transmit HDMI at 1.08GHz through regular DDR-DQ pins.)

It is probably the same with Spartan unless you use LVDS dedicated transmitters which are balanced low voltage outputs.  LVDS usually means 1.8 or 1.5v output, but 2 of them per channel which will need a differential receiver to amplify each channel. Spartan 7 is a faster FPGA than CycloneIV/MAX10.  I would only choose MAX10 if you want low power and no bootprom as 16 NCOs running at 100MHz driving a 10:1 serdes transmitter would only draw something like 50-100ma VCC on a Cyclone/Max10.  Though, the MAX10 will require a compiler workaround to run it's outputs at 1GHz.

[langwadt]

Do any of the regular pins on spartan 7 work in that 1Gbps mode?

afair SERDES and  DDR is available on all pins (~1Gbps need LVDS so pair of pins)

[hamster_nz]

Do any of the regular pins on spartan 7 work in that 1Gbps mode?

afair SERDES and  DDR is available on all pins (~1Gbps need LVDS so pair of pins)

But when you are generating a square wave at about 1MHz +/-50kHz then a single-ended output buffer will be just fine.