Electronics > FPGA

NCO to generate square wave

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I need to produce N (probably less than 16) number of square waves, fixed 50% duty cycle with frequency of 1MHz, but each independently variable in frequency with steps of no more than 100Hz, within ~50kHz on either side of 1MHz.

Are N channels of numerically controlled oscillator (NCO) blocks within FPGA a plausible method to do this?

I found a VHDL snippet here https://gist.github.com/RickKimball/45d0753a900f92d5fdd836746062588c that seems to be rather compact.

all you need is an adder per output, the MSB is you squarewave

but you will have jitter of +/- a clockcycle

Skyworks (formerly Silicon Labs) has several clock generator chips with multiple outputs. Many with 8, a few with 12.


A resolution of 100 Hz? Wow. The difference between the period of a 1 MHz signal and 1 MHz + 100 Hz is just about 100 ps.
You can get an average frequency with that resolution using the technique mentioned above without requiring an actual resolution of 100 ps (which would require a base clock of 10 Ghz!!), but then you'll get inevitable jitter. What is the acceptable jitter here?

If you want jitterless, then you will end up having to use long-division low frequency phase comparator (like 100hz) PLLs designed for this purpose.  Though, you would need 16 of them and an MCU to control all or for the strict phase comparator with VCO, you would need an FPGA to generate all 16 reference 100hz output signals + the high frequency 1MHz signals.

Using a DDR trick with CycloneIV/MAX10, I have generated 1ns step accurate (equivalent to a 1GHz base clock) outputs running the core clock at 500MHz.  Since you need 100ps, as SiliconWizard said, you would need an FPGA with a 10gbps transmitter to pull this off with 0 added jitter where as my trick would generate an additive corrective 1ns jitter once every 1-9 output toggles unless you tune the output right on any integer 1000hz offset of 1MHz.


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