On Xilinx 6 or 7 series the SelectIO SERDES is good to about 1Gb/s.

500 bits on, 500 bits off gives 1.000MHz

499 bits on, 500 bits off gives 1.001MHz (not perfectly square duty cycle, but near enough)

499 bits on, 499 bits off gives 1.002MHz

That is with minimal jitter.

499 bits on, 500 bits off, followed with nine blocks of 500 bits on, 500 bits off = 10 pulses over 9,999 cycles = 1.000100 MHz with some jitter

If that meets your needs, then it is perfectly achievable with a little bit of actual design work.