Net 'myled' does not have a driver?

[ali_asadzadeh]

This is some very simple Code for a gowin FPGA,
Do you know why I got this warring at synthesize output?

Code: [Select]

module Top
  (input clk,
    output led);

reg [23:0] CNT = 0;
reg myled = 1'b1;



always @(posedge clk) begin
   
  CNT <= CNT + 1'b1;

  if(CNT == 25000000) begin
    myled <= !myled;
    CNT <= 0;
  end
end

assign led = myled;

endmodule

WARN  (EX2998) : Net 'myled' does not have a driver
WARN  (CV0003) : Output "led" has undriven bits, assigning undriven bits to 0, simulation mismatch possible

So the output pin would not drive the LED 

[asmi]

Not all FPGAs have ability to pre-set flip-flops during configuration, which is why it's recommended to have explicit reset sequence unless you target devices which are known to have such functionality.

[ali_asadzadeh]

Why don't you just "reg myled" and skip the assign statement? I've been writing this way since my first day with FPGAs, and it's always been working.

How?
You mean by saying like this

Code: [Select]

module Top
  (input clk,
    output  reg led);
Gowin EDA complains about this type of code

[FenTiger]

This is some very simple Code for a gowin FPGA,
Do you know why I got this warring at synthesize output?

Code: [Select]

reg [23:0] CNT = 0;


If CNT can range from 0 to 16,777,215 decimal...

Code: [Select]

  if(CNT == 25000000) begin
    myled <= !myled;


...then the if here is always false, and the only statement which assigns to myled can never happen.

[ali_asadzadeh]

Not all FPGAs have ability to pre-set flip-flops during configuration, which is why it's recommended to have explicit reset sequence unless you target devices which are known to have such functionality.

How? I do not have any additional IO in my PCB for Reset.

[ali_asadzadeh]

If CNT can range from 0 to 16,777,215 decimal...

This was the problem, I changed the CNT size to

Code: [Select]

reg [24:0] CNT = 0;Now it's working.

[ali_asadzadeh]

module top(int foo, output bar);
reg bar;
...
endmodule

This works too, with the change in CNT size,But this type of declaration would throw another warning too

Code: [Select]

WARN  (EX3628) : Redeclaration of ansi port 'led' is not allowedBut the code works on the FPGA

[ali_asadzadeh]

Here is another example, Testing baudrate generation
The output LED is always 0


The Top Module

Code: [Select]

module Top
  (input clk,
    output led);

BaudGenerator #(.Baud(2)) myBaudGen  (.i_clk(clk),.o_baudTick(led));



endmodule
BaudGenerator Module

Code: [Select]

module BaudGenerator
#(
    parameter Baud = 9600, //Default Baud rate 
    parameter sysClk = 25000000) //System frequency
(
    input i_clk,
    output reg o_baudTick
);

    localparam  [23:0] c_baudAddValue = (16777216.0 * Baud * 4.0) / sysClk;
    //reg [23:0] c_baudAddValue = (16777216.0 * Baud * 4.0) / sysClk;
    reg [23:0] r_baudCnt = 0;
    reg [1:0] r_baudEdge = 0;

    always @(posedge i_clk ) begin
        r_baudCnt <= r_baudCnt + c_baudAddValue;
        r_baudEdge[1] = r_baudEdge[0];
        r_baudEdge[0]= r_baudCnt[23];
        o_baudTick <= 0;
        if (r_baudEdge[1] == 1'b0 && r_baudEdge[0] == 1'b1) begin
            o_baudTick <= 1'b1;
        end
    end

endmodule


[ali_asadzadeh]

I just tried it, and it works as expected!

I think Yosys uses the same trick to initialize registers to 1, as posted somewhere in Clifford/Claire's blog some time ago.

Thanks, Just show me your code