New FPGAs from Renesas

[ataradov]

Renesas is releasing new FPGAs via Dialog Semiconductor that they've acquired some time ago.

Here is a press release https://www.renesas.com/us/en/about/press-room/renesas-enters-fpga-market-first-ultra-low-power-low-cost-family-addressing-low-density-high-volume

The ForgeFPGA Family will serve applications that require less than 5,000 gates of logic, with initial device sizes of 1K and 2K Look Up Tables (LUTs). Standby power of less than 20 microamps is projected for the first devices, about half the power of competing devices. Users will be able to download the development software at no cost and with no license fees. The software offers two development modes to accommodate both new and experienced FPGA developers: a “macrocell mode” that uses a schematic capture-based development flow, and an “HDL” mode that provides a familiar Verilog environment for FPGA veterans.

Key Features of the ForgeFPGA Family
* Very low power as low as 20 microamps standby
* Very low price in volume of well under US$ 0.50
* Free, downloadable software with no license fees that includes both schematic capture and HDL modes
* Proven ability to deliver very high volumes
* Renesas is preparing to offer multiple Winning Combinations featuring the new ForgeFPGA devices with complementary MCU, analog, power and timing devices. Winning Combinations provide an easy to use architecture, simplifying the design process and significantly reducing design risk for customers in a wide variety of applications.

ForgeFPGA engineering samples are available now, along with beta design software and a prototype development kit. The first ForgeFPGA device, the 1K LUT offering, is expected to be available in production quantities in Q2 2022. Interested designers can visit https://www.dialog-semiconductor.com/products/greenpak/low-power-low-cost-forgefpga to find out more.

I wonder if they plan to make them easily accessible to general public. Neither Dialog or Renesas were particularly hobby-friendly.

[SiliconWizard]

They could "compete" with the Lattice iCE40 series for instance (more precisely, iCE40 LP.)
Curious to see more.

[ataradov]

It all really depends on the availability of tools and documentation to common public. Lattice is very good in this respect.

But "Winning Combinations" suggest that marketing team was heavily involved, so in reality things may not be as great as described.

[DiTBho]

or vhdl
or nothing
 

[mon2]

Cool. Download the latest toolchain to start developing with the FPGA. Have emailed our local rep @ factory for more details. Unless protected under NDA, will share the details once received.

See attached from the latest tool just downloaded.

[ataradov]

Yep, works with Linux too. Supplied as a normal package, no node locks or anything like this. Download form accepts bogus info, including email.

If the devices are indeed cheap and available this will be a very interesting device.

And synthesis is done with Yosys. This is great!

The default 16-bit PWM module synthesized and reports 73 MHz as a maximum achievable frequency. This would require a bit of poking around, but it looks like the performance is close to similar lattice devices.

Not a huge fan of a separate VDDIO/VDDCORE supplies. I guess as long as there are no stupid sequencing requirements.

[ataradov]

One thing I can't figure out is the package. I really hope it is not some weird proprietary nonsense. There seem to be 24 pins, but presence of pins 7/GrP2, 8/GrP1 and 9/GrP0 makes me suspicious.

Although device picture seemingly shows QFN-24 and the dimensions are shown as 3x3 mm, which matches QFN-24-0.4mm.

Also, in the part selector (where you can only select one part for now), it says that it is an OTP device. I assume it is possible to load SRAM configuration many times though the interface and only embedded memory is OTP, but still sounds like a limitation. Looking at other devices, there will probably be an MTP version.

[nctnico]

These devices look extremely interesting and the tools not needing any node locked license nonsense is a big plus. Any support for VHDL?

[ataradov]

Yosys only fully supports Verilog. There is some work on VHDL, but I'm not fully sure of its status, but I'm sure it is not production ready. And since they are using Yosys, I would not expect VHDL. I see no obvious mentions of VHDL in the IDE anywhere.

But the devices are not that complicated, you can't write too much code anyway.

The tools look great. Clean and fast. For now this looks like a beginner-friendly IDE that also does not limit professionals should look like.

Although just like with Yosys workflow for Lattice, I see no way to specify constraints. It looks like it the the case of "you get what you get".

[tszaboo]

I'm going to guess:
- NDA required
- not available from Digikey, Mouser or anyone
- No license fee, but yiou have to sign up for the free license
- 2/3 row flipchip BGA
- Pricing based on how much you want it

[ataradov]

NDA for what? We are already playing with the IDE, it is free to download and it generates bit files just fine. The devices are too small to have some extensive library of IP that needs to be licensed.

The package is QFN-24 for the first device that is supposed to be available.

It is also the best IDE I've seen from any FPGA vendor. And given yosys workflow, I assume command line would not be a problem either.

[YurkshireLad]

I know next to nothing about FPGAs, but I'm very interested in these. It'll be a great entry point for me if they turn out to be half usable with a good tool chain. Exciting!

[EEVblog]

Who do I have to contact to get one of these kits?

EDIT: Found an old contact at Dialog who wanted to do sponsored content on the blog, have asked them about the dev kit.

[SiliconWizard]

And given yosys workflow,

Does it really use yosys? That'd be the first commercial tool doing this that I know of.

[ataradov]

Does it really use yosys? That'd be the first commercial tool doing this that I know of.

Yep. And it is not some rebranded stuff, it says it everywhere in the logs.

I bet they did not want to bother inventing tools for small FPGAs like this. Too much effort for too little benefit.

[SiliconWizard]

Does it really use yosys? That'd be the first commercial tool doing this that I know of.

Yep. And it is not some rebranded stuff, it says it everywhere in the logs.

I bet they did not want to bother inventing tools for small FPGAs like this. Too much effort for too little benefit.

That's interesting. And it's not really about inventing tools either: a lot of vendors actually use Synopsys Synplify for synthesis - so they do not design their own synthesis tool. Some have - XIlinx has XST, for instance - while others don't (IIRC, but I haven't used that in a few years, Actel/Microsemi only had Synplify), and yet some others have both (Lattice offers both their own tool, LSE, and Synplify...)

It probably has a lot to do with licensing and cost reasons. Synplify is not free.

Now I wonder what tool they use for place-and-route. Is this nextpnr (the "de facto" friend of yosys), or is it their own tool?

[ataradov]

Now I wonder what tool they use for place-and-route. Is this nextpnr (the "de facto" friend of yosys), or is it their own tool?

They use something called "eda-palcer". The tool does not accept any standard version or help parameters (-h, --help, -v), saying "Incorrect Input" and does not print any information when launched. So I assume it is something custom.

[Cerebus]

best IDE I've seen from any FPGA vendor. And given yosys workflow, I assume command line would not be a problem either.

Depends what they use for place and route, and bitstream generation. They could have made those non command line accessible - it would be stupid with yosys in front, but I've seen dumber mistakes made. It would be a shame have they gone down that route, and on the flip side it would be very cool if they've also leveraged NextPNR or similar for the place and route and just not mentioned it. (Literally immediately before I read the above and typed this I've been bashing away on an iCE40, all with the open source tool chain without a vendor tool in sight. Bliss, edit the source, save it, type "make prog" and hit the reboot switch once it's finished flashing the eeprom.)

Edit: crossed with Alex's post but can't be bothered to edit.

[ataradov]

The placer is a standalone tool, but it does not accept any random parameters, and in the logs they don't show what parameters they are supplying. But I'm sure this is not out of malice, the tool is just new. It would not be too hard to figure that out anyway - just make a dummy tool that prints all the arguments.

I did the tool, and it looks like they are trying to hide something. The tool takes two parameters - one encrypted looking string and then a number:

Code: [Select]

AAABqnjafY1BS8MwGIaj4tmDuJOg4EUPaZP5C7IsdqFZGrIUttPHdKkWNltYhf58s5nepIeH9/u+9yFBCE0QQteBp8BV4DnmS+A+cBF4jDnsDzFvY05i3gUuAzenN7Df1VX61Rx8ut37Pq3az236/lPvd9D5Y5d2hzY5KbhqR6w3kzGaA+1pUrW4bkbUuoFj6z+g/k66vsNCs5kSMJNu5axgSyhKZ0oHbC3pWAnccjIIC5ktYC70SroNGMZzqTP6bymLoSeYqxx4oXlprdAOCuMoNopxAUzPwVnJFNjwoyDYaBsP0okwFo6pKcFLtv4zzudXQn4BAyBssQ== and 23111.

The string is the same for the same inputs though. And this string includes full paths. So running the tool from a completely different directory with this string as a parameter successfully produces the bitstream file.

[SiliconWizard]

Well, now I'm a little less surprised, then...

[ataradov]

I hope they are doing it for the sake of not having to deal with encoding of slashes in the path for different OSes or something like this, and not some evil reason. I really see no point in hiding that stuff, since all you have to do is run the IDE once on a specific PC with a specific path location and you will get the string for the Makefile.

But also, if those devices are available, there will be support added to open source tools.

[asmi]

Code: [Select]

AAABqnjafY1BS8MwGIaj4tmDuJOg4EUPaZP5C7IsdqFZGrIUttPHdKkWNltYhf58s5nepIeH9/u+9yFBCE0QQteBp8BV4DnmS+A+cBF4jDnsDzFvY05i3gUuAzenN7Df1VX61Rx8ut37Pq3az236/lPvd9D5Y5d2hzY5KbhqR6w3kzGaA+1pUrW4bkbUuoFj6z+g/k66vsNCs5kSMJNu5axgSyhKZ0oHbC3pWAnccjIIC5ktYC70SroNGMZzqTP6bymLoSeYqxx4oXlprdAOCuMoNopxAUzPwVnJFNjwoyDYaBsP0okwFo6pKcFLtv4zzudXQn4BAyBssQ== and 23111.

This string looks like a base64 encoded binary data. So it could be just a bunch of parameters passed into the tool. I've seen this approach used when you want to pass some complex data structure which does not easily map to a regular parameter string.

[ataradov]

Yes, but all base 64 decoders I tried fail to decode it. I have not tried too hard though.

Changing a single number in the settings results in a lot of changes in the output, but not entire output is changing. And changes are in chunks spread over the string.

And the number changes too, so it might be some sort of check sum, but the tool just ignores it, any number or string works as a second parameter. It just must be present.

[asmi]

These parts would be great as a system controller for my FPGA boards. Right now I have to use micros, but they are overkill as the only thing I need from them is to bang in some initialization data via I2C or SPI to PMICs, and control power rail sequencing. I hope they will make them available in reasonable packages, like 0.8+ mm BGA with say 40-50 GPIO split into two Vccio banks and the rest for power/gnd. Something like a full-matrix 64 ball (8x8) BGA would be ideal for my needs.

[SiliconWizard]

The smallest iCE40 and MachXO2/3 from Lattice are good fits for similar applications. It's not like the products don't exist yet.