New FPGAs from Renesas

[julian1]

Also, as I noted with yosys for ICE40, there is seemingly no way to specify any timing constraints.

Do you mean per net/pin?  icetime will report global propagation time, and max clk speed of the design.

[ataradov]

It will report maximum frequency, but there is no way to specify the limits so that design can be driven by those limits. And there is no way to specify desired setup/hold times. You just get what you get.
 

[rstofer]

I doubt they will be available to general public for at least a year. I would not ge too excited.  And getting retail price in current conditions is even more problematic.

They got back to me about the dev kit.
They are rare as hens teeth and they could possibly loan me one for a short time if I really wanted it. But I said I'll wait until it's generally available otherwise there isn't much point doing a video on it on something no one can get.

It seems to me that the most important selection criteria is development software with an unlimited license.  I went through the debacle when UCSD canceled the Pascal licenses and it was ugly.  I stayed away from Atmel for years because the terms of the license included a clause where they could cancel the license at any time for any reason or no reason at all.  I'm not going to spend any time or money on a device that uses a toolchain that can be yanked at any time.

The next criteria would be the availability of several levels of development boards - exactly like what I can get from Digilent.  I can get an Artix 7 board in several flavors with varying amounts of IO and gadgets.  Personally, I want a LOT of gadgets: 7 segment displays, pushbuttons, slide switches, GPIO and, by all means, onboard programming via USB.

In a distant third place is price.  Yes, the boards I select are expensive but I'm only going to buy one (maybe two) and they can be serially reused for future projects.  I look at the cost as 'future proofing'.  But that's just me.

Yes, I'm stuck in the Xilinx camp but I have played with the Lattice ICE40HX1K-STICK-EVN and it's a nice, albeit small, board for $49  (Out Of Stock at DigiKey).

https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/ICE40HX1K-STICK-EVN/4289604

I prefer the Digilent A7 board even though it is 4 times as expensive.  It has more than 4 times the the utility as well and I buy the 100T variant.

https://digilent.com/shop/boards-and-components/system-boards/fpga-boards/

I also have the Basys 3 and Arty boards along with the Cmod A7 but the Cmod is only available in a 35T variant.  I like the virtual dumpster idea and prefer the larger chips even though I don't really need them.

I seem to be stuck in Xilinx land...

As I said above, price is my 3rd place selection criteria.

[asmi]

I use Xilinx chips as a main processing device as well, but here we're talking about small auxiliary chips for supporting the main one, like bootstrapping programmable DC-DC converters, controlling power-up/power-down rail sequencing, generating reset pulse, things like that. You needs must be really modest for these devices to work as main processing unit.

[ebclr]

Forget Renesas, The only thing they do well, it's ignore you

[DiTBho]

Very bad experience with their MPUs

[gnuarm]

Not a huge fan of a separate VDDIO/VDDCORE supplies. I guess as long as there are no stupid sequencing requirements.

Then you should stick to PLDs.  I don't know of any complex device in the last 20 years that wasn't dual supply or more. 

[gnuarm]

I'm going to guess:
- NDA required
- not available from Digikey, Mouser or anyone
- No license fee, but yiou have to sign up for the free license
- 2/3 row flipchip BGA
- Pricing based on how much you want it

People seem to be keying in on Renesas and ignoring Dialog.  Dialog has been selling the GreenPak programmable device line for some time now and while their business model is for them to supply production quantities by preprogramming the chips, they have always been supportive of users.  You can buy devices from Mouser, so I expect to see the FGPAs from Mouser as well. 

Of course pricing is based on quantity.  Who doesn't do that???  We will see what packaging they provide.  If they are shooting for the mobile device market where miniaturization is king, I expect they will be in flip chip, but they sell the GreenPak devices in QFN and also TSSOP, so we may be surprised by packaging supporting simple soldering and low cost board fab.

[gnuarm]

Does it really use yosys? That'd be the first commercial tool doing this that I know of.

Yep. And it is not some rebranded stuff, it says it everywhere in the logs.

I bet they did not want to bother inventing tools for small FPGAs like this. Too much effort for too little benefit.

Tools are the expensive part of selling FPGAs.  Only the big suppliers write their own tools.  Everyone else licenses synthesis software which costs them for every copy they supply.  Now you know why many companies don't want to support no-profit hobbyists. 

Has anyone looked at simulation?  I'm not familiar with Yosys, but I assume that is just synthesis.  Are they also supplying open source simulation or are you on your own to figure that out?  When using Gowin they punted on the simulation.

[ataradov]

Then you should stick to PLDs.  I don't know of any complex device in the last 20 years that wasn't dual supply or more. 

MAX10 from Intel/Altera, Lattice XO2.

MAX10 specifically has a version with internal core voltage regulator and with external. And that's a good way of doing things. While some designs may need flexibility with bank voltages and core supplies, many are just strictly 3.3V and having a convenience of dealing with just one supply is nice. And all they need to do for this is include an LDO inside the device. It may need external passives, that's fine, of course.

[nctnico]

Does it really use yosys? That'd be the first commercial tool doing this that I know of.

Yep. And it is not some rebranded stuff, it says it everywhere in the logs.

I bet they did not want to bother inventing tools for small FPGAs like this. Too much effort for too little benefit.

Tools are the expensive part of selling FPGAs.  Only the big suppliers write their own tools.  Everyone else licenses synthesis software which costs them for every copy they supply.  Now you know why many companies don't want to support no-profit hobbyists. 

Has anyone looked at simulation?  I'm not familiar with Yosys, but I assume that is just synthesis.  Are they also supplying open source simulation or are you on your own to figure that out?  When using Gowin they punted on the simulation.

You can use GHDL which works OK. I did run into funny effects though when assigning a clock to a different signal; in that case GHDL likes to delay the new signal as well as if it is registered by the clock. But this could be a bug in an older version.

[woofy]

Has anyone looked at simulation?  I'm not familiar with Yosys, but I assume that is just synthesis.  Are they also supplying open source simulation or are you on your own to figure that out?

yosys for synthesis, nextpnr for place n route.
for verification I use iverilog/vvp and gtkwave.

[gnuarm]

The smallest iCE40 and MachXO2/3 from Lattice are good fits for similar applications. It's not like the products don't exist yet.

Not even close. Their packages options are TERRIBLE. I want something like 7x7 mm 64 ball BGA 0.8 mm pitch. There is nothing in their lineup of that kind of size - either you get much smaller part (with super-expensive HDI tech required to use them, no thank you), or you go for a ridiculous overkill of 256 ball version.

So you want a Goldilocks BGA part.  Fair enough.  We all want what's optimal for our work. 

There is also ICE40HX8K-BG121 in BGA-121 0.8 mm pitch package, but it's been out of stock everywhere I looked for a while. So no dice here either. Leaded packages are not good for me because they take too much space, and space on 6+ layer boards is expensive so I'd rather not waste it if it can be helped.

I've never considered that BGAs are any better for board space than leaded parts.  It is very hard to place BGAs close to one another as they often require space for breakout and routing.  A leaded part typically has room under the part to help breakout and routing, so little extra room is needed on the board.  I've had to consider replacing a 20 pin TSSOP with a 24 pin QFN and it's not really much different, especially with a grounded thermal pad.  The part becomes a roadblock for routing.  BGAs are often the same sort of thing since the inner balls require vias under the part to break out.  So even if they are smaller than a similar leaded part, they end up using similar board space. 

Right now I use STM32H723VGH6 MCUs (which is the gross overkill) because they were the only ones I was able to get my hands on at the time. Hopefully availability will improve soon, so that I will be able to use something more fitting for my needs, but for now I'm forced to use whatever I can manage to procure.

I'm not familiar with this concept... MCUs outside of an FPGA.  What do you put IN your FPGAs?  lol

[gnuarm]

Yes, unfortunately Lattice parts either come in large packages or very-fine pitch ones.
There are some QFN packages, but the number of IOs may be too limited for a particular use (I think their largest QFN is 48 pins?) So of course all depends on your particular project... Now when you have nothing else available with similar features and price range, you may go for the ~200-pin, 0.8mm BGAs, even when that means using only 1/3 of the pins...
I'm sure curious to see when those new chips from Renesas will be available, and if they will be at the prices and packages that have been announced...

Crosslink-NX has a 72QFN package. Comes as a 17K or 39K 4-input LUT FPGA, with additional large block RAM similar to ice40. The logic density gets it up there with some of the ECP5 stuff (I also believe similar architecture), but without the BGA stuff. Unfortuntely.. I think they're also out of stock.

Anyway, these small FPGAs also attract my attention. Lattice also has low quiescent power listed for their MachXO(2/3) series of FPGAs in freeze mode, especially on the low logic density ones. I'm actually looking at a new application that would benefit from an (nearly) always-on FPGA with some amount of logic (say 1-4K LUTs) to act as an experimental IOT design. However, for the larger Lattice chips, their quiescent current ramps to nearly 100uA.

I don't often care so much about "freeze mode" specs.  I'm looking for low quiescent power as well as low per MHz power so clocking at low speeds gets you about quiescent power levels.  Some logic in various designs can run from a 32 kHz clock with virtually no dissipation... if the chip properly supports it.  Things like "freeze mode" typically require the entire chip to be shut down.

20uA quiescent supply current at e.g 1 or 1.1V would do the job. But I'll have to see (or look up) if that also is a figure for only their smallest FPGAs (I believe their datasheet was inconclusive at best about it)

I believe some of the newer Lattice iCE40 devices get close to that number, less than 50 uA anyway.  The original SiliconBlue 65 nm devices had below 100 uA quiescent current and the iCE40 parts were supposed to be even lower, but when Lattice bought them and they moved to 40 nm the current went up.  Don't know if that was because they were never going to be able to achieve the really low currents they talked about or if Lattice imposed some restriction that required the number to be higher.  Heck, it could be as simple as the parts were exactly what they expected, but Lattice wanted more margin in the spec so it wouldn't be the cause of rejecting any parts or maybe they no longer needed to bother testing that spec with a relaxed figure.

[asmi]

I've never considered that BGAs are any better for board space than leaded parts.  It is very hard to place BGAs close to one another as they often require space for breakout and routing.  A leaded part typically has room under the part to help breakout and routing, so little extra room is needed on the board.  I've had to consider replacing a 20 pin TSSOP with a 24 pin QFN and it's not really much different, especially with a grounded thermal pad.  The part becomes a roadblock for routing.  BGAs are often the same sort of thing since the inner balls require vias under the part to break out.  So even if they are smaller than a similar leaded part, they end up using similar board space. 

Well just compare 64/100 pin QFN/QFP package size with BGA with the same ball count, and you will see the difference very clearly. It's even worse for higher pin count.

I'm not familiar with this concept... MCUs outside of an FPGA.  What do you put IN your FPGAs?  lol

FPGA is the main processing device, but a board often requires a sort of system controller which would orchestrate all HW pieces together - like programming DC-DC converters, power rail sequencing, cooling management, etc., which are either impossible or impractical to implement inside FPGA. FPGA itself typically does the actual functionality - video processing, DSP, etc - whatever is the main function of a board.

[ataradov]

Has anyone looked at simulation?  I'm not familiar with Yosys, but I assume that is just synthesis.  Are they also supplying open source simulation or are you on your own to figure that out?  When using Gowin they punted on the simulation.

I just tried. They have simulation functionality in the "IDE", but I could not make it work. I'll have a closer look.It asks you to create a test bench to run the simulation, but after that nothing happens. I don't see any outputs or waveforms.

At the same time I noticed one more thing. Your code is not actually stored as files. It it stored in the same "encrypted" form as a string inside the main project file. So the whole project is just one file, including  test benches.  This further shows that they are not going after "grown up" FPGAs.

[gnuarm]

I don't want to sound like a Lattice salesman

Not at all. I too like Diamond the most from all. It is still a node locked full blown IDE. And every year you have to ask them for the license. In this case "IDE" is more like Arduino compared to big IDEs for MCUs. It is bare-minimum that just works. And super fast synthesis times are also pretty cool. It is probably not something you want for a device with more than 1K LUTs though. So I don't know how it will scale.

Also, as I noted with yosys for ICE40, there is seemingly no way to specify any timing constraints. So, I'm not sure how that would work in practice. I'd be interested to try though.

I've used the Diamond software for a long time and have a current product I have to support that was developed with it.  But didn't they end support for the older software or something?  I recall that about a year ago I downloaded my last possible license file and I suppose that is running out about as we speak.  I have a new computer now so it probably won't work anymore anyway.  I think it was locked to the hard drive ID which I want to say can be rewritten. 

This is the sort of crap you get into with licensed software even if they give it away. 

At least it shows the chip is real and not vapourware. And Dave could give the software a whirl. I hope VHDL support gets added quickly or maybe it already is.

I would not wait for VHDL in this case.

I would have said the same thing about Gowin, but their VHDL came out and works fine.  But I suppose they were at least talking about it coming soon.  Does Dialog mention any plans for VHDL?  I don't think they ever considered it for their GreenPak parts.

[gnuarm]

The devices are so small and have so little going for them that the language does not really matter. Some people will not use it out of principle or preference, but I don't think it will affect industry acceptance at all.

It depends on the markets they are after.  The telecomms market is Verilog pretty much 100%.  Some European markets and US defense are VHDL.  I doubt this will get much use in the US defense market no matter what.  I don't know enough about European VHDL use to know if there might be much market acceptance with this part or not. 

While I would not avoid a part because of the language support, I've never had to use anything other than VHDL except for a short stint working at a telecomm test gear manufacturer.   Describing RTL functionality doesn't take much knowledge of either language.

[gnuarm]

Then you should stick to PLDs.  I don't know of any complex device in the last 20 years that wasn't dual supply or more. 

MAX10 from Intel/Altera, Lattice XO2.

MAX10 specifically has a version with internal core voltage regulator and with external. And that's a good way of doing things. While some designs may need flexibility with bank voltages and core supplies, many are just strictly 3.3V and having a convenience of dealing with just one supply is nice. And all they need to do for this is include an LDO inside the device. It may need external passives, that's fine, of course.

I don't know about the Altera devices, but the Lattice parts are dual voltage, they just allow you to use internal regulators for the core voltage or not.  I have a design using the XP devices and when I needed to switch from a single voltage part to a dual voltage part I found out they are the same die.  They add a bond wire that tells the part to enable/disable the regulators and you have to twiddle a bit in the programming files so the programmer recognizes the ID which also changes a bit. 

My point is you might only need one regulator voltage, but the parts have at least two sets of voltage pins and sometimes more. 

[gnuarm]

Tools are the expensive part of selling FPGAs.  Only the big suppliers write their own tools.  Everyone else licenses synthesis software which costs them for every copy they supply.  Now you know why many companies don't want to support no-profit hobbyists. 

Has anyone looked at simulation?  I'm not familiar with Yosys, but I assume that is just synthesis.  Are they also supplying open source simulation or are you on your own to figure that out?  When using Gowin they punted on the simulation.

You can use GHDL which works OK. I did run into funny effects though when assigning a clock to a different signal; in that case GHDL likes to delay the new signal as well as if it is registered by the clock. But this could be a bug in an older version.

Not sure what you mean by "assigning a clock to a different signal".  If you mean literally just writing

Code: [Select]

clk1 <= clk2;
in VHDL that will create a delta delay which will in essence be a new clock domain slightly out of sync with the first.  So register outputs will be updated on clk2 before clk1 gets it's edge and cause unexpected results.

This is not a bug, it's a feature... really!

[ataradov]

they just allow you to use internal regulators for the core voltage or not.

And that's fine. I just don't care to have more power supplies on the board that need to be sequenced correctly for things to work.

[gnuarm]

I've never considered that BGAs are any better for board space than leaded parts.  It is very hard to place BGAs close to one another as they often require space for breakout and routing.  A leaded part typically has room under the part to help breakout and routing, so little extra room is needed on the board.  I've had to consider replacing a 20 pin TSSOP with a 24 pin QFN and it's not really much different, especially with a grounded thermal pad.  The part becomes a roadblock for routing.  BGAs are often the same sort of thing since the inner balls require vias under the part to break out.  So even if they are smaller than a similar leaded part, they end up using similar board space. 

Well just compare 64/100 pin QFN/QFP package size with BGA with the same ball count, and you will see the difference very clearly. It's even worse for higher pin count.

That's my point.  If you only compare package size you aren't doing a fair comparison.  The entire area around the BGA used for breakout routing needs to be considered.  The BGA ends up being a big road block to other routing while the QFP has room under it for vias, etc.

I'm not familiar with this concept... MCUs outside of an FPGA.  What do you put IN your FPGAs?  lol

FPGA is the main processing device, but a board often requires a sort of system controller which would orchestrate all HW pieces together - like programming DC-DC converters, power rail sequencing, cooling management, etc., which are either impossible or impractical to implement inside FPGA. FPGA itself typically does the actual functionality - video processing, DSP, etc - whatever is the main function of a board.

I tend to design systems where the FPGA is the SoC doing all the work.  Besides, it was a rhetorical question.  Didn't you see the lol? 

[gnuarm]

Has anyone looked at simulation?  I'm not familiar with Yosys, but I assume that is just synthesis.  Are they also supplying open source simulation or are you on your own to figure that out?  When using Gowin they punted on the simulation.

I just tried. They have simulation functionality in the "IDE", but I could not make it work. I'll have a closer look.It asks you to create a test bench to run the simulation, but after that nothing happens. I don't see any outputs or waveforms.

At the same time I noticed one more thing. Your code is not actually stored as files. It it stored in the same "encrypted" form as a string inside the main project file. So the whole project is just one file, including  test benches.  This further shows that they are not going after "grown up" FPGAs.

That makes no sense.  You are saying the test bench file is not stored as text?  Or that all of the source files are not stored as text?  Either way there must be a way to have text files instead.  I can't imagine any company being willing to write IP and not be able to port it to some other device if these parts aren't suitable for any of a variety of reasons down the road. 

[gnuarm]

they just allow you to use internal regulators for the core voltage or not.

And that's fine. I just don't care to have more power supplies on the board that need to be sequenced correctly for things to work.

The board I designed with the Lattice part was designed for either chip.  So it has a second power regulator, a tiny 6 pin package and ways to wire up either version.  This has served me well allowing me to use whichever version of the part was available.  At this point both versions are going away, so I'm building the last 10,000 units.  The first 2,000 of these are dual voltage and the last 8,000 will be single voltage.  Arrow is the last source of these parts and after some 5 or more years they are reaching the point of running out... and prices are going up.

[ataradov]

That makes no sense.  You are saying the test bench file is not stored as text?  Or that all of the source files are not stored as text?

Nothing is stored as text. The whole project is just one file that contains everything. I think this supports their business model where you do the design, send it to them and they ship you the programmed devices.

There is no way to edit text files. You get the IDE and that's it.

Again, this feels more like Arduino that any other FPGA IDE. This is designed for very simple things.

So, yes, the whole thing makes less and less sense. Hopefully this device will just be supported by open source tools to make it usable.