Numato Labs Mimas A7 Mini FPGA Development Board - your experiences?

[JohnnyMalaria]

Hi,

I just received a Numato Labs Mimas A7 Mini FPGA Development Board and would like to know your experiences with it.

https://numato.com/product/mimas-a7-mini-fpga-development-board/

Thanks,

John.

[SiliconWizard]

No experience with this one, but I have a couple older boards from Numato (Saturn V3 and Mimas), respectively with a Spartan 6 LX45 and LPDDR, and  a Spartan 6 LX9 with no external RAM (but was cheap, like $30).

Both boards were fine. I'm still using the Saturn V3 currently (for prototyping my RISC-V core and peripherals), no problem whatsoever.

[FlyingDutch]

Hello,

I also have two older boards of Numato Lab: Elbert v.2(Spartan3A):

https://numato.com/product/elbert-v2-spartan-3a-fpga-development-board/

and Mimas V2 (Spartan6):
https://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram/
 
They both were very good. I have especially sentiment for Elbert v.2 (Spartan3A) board, because it was my first in live FPGA board.

Best Regards

[DiTBho]

Saturn V3

it it this one the one you were talking about fast-usb transfer?
it there any available example?

[SiliconWizard]

Saturn V3

it it this one the one you were talking about fast-usb transfer?
it there any available example?

Possibly so. It indeed has an FT2232H on board, with (contrary to many other boards) all pins required for parallel mode access (FT245 async) routed to the FPGA. So you can use it in this mode (instead of just UART, which is very common on many other dev boards). In this mode you can get around 8 MBytes/s. So yeah I'm using that to read and write from a PC. Sending code through USB with this is already very fast compared to using an UART.

The 'clock out' pin of the FT2232H is not routed to the FPGA though, so you can't use it in parallel synchronous mode, which would allow up to ~30 MBytes/s. Of course that can always be done with an external FTDI breakout board...

I don't have code available that would be ready for consumption, but this is very easy to interface. It's just a FIFO. Read the FT2232H datasheet and you'll probably figure it out in no time.

[cfbsoftware]

We recently ported our Astrobe Embedded Project Oberon System to the Mimas A7 Mini without any problems. It is useful that the two 12-pin connectors are compatible with Digilent's Pmod modules because we can use an adapter board that we have designed for Digilent boards (e.g. the Arty range) to access an SDHC card, two PS/2 ports and a monochrome VGA socket.

All we need now is a daughterboard with 1 Mbyte of 10ns 32-bit SRAM and then we could port the Project Oberon Workstation as well. There are 70 spare IO so it would be feasible - the SRAM needs at most 32 data, 18 address and 6 control lines. A suitable RAM chip is the IS61WV25616BLL-10TL from ISSI. These are 256K  x 16 so two would be required. Unfortunately the design of such a board is beyond our expertise so we'd be interested to know if anything already exists that could be used with the Mimas A7 Mini.

[SiliconWizard]

We recently ported our Astrobe Embedded Project Oberon System to the Mimas A7 Mini without any problems. It is useful that the two 12-pin connectors are compatible with Digilent's Pmod modules because we can use an adapter board that we have designed for Digilent boards (e.g. the Arty range) to access an SDHC card, two PS/2 ports and a monochrome VGA socket.

All we need now is a daughterboard with 1 Mbyte of 10ns 32-bit SRAM and then we could port the Project Oberon Workstation as well. There are 70 spare IO so it would be feasible - the SRAM needs at most 32 data, 18 address and 6 control lines. A suitable RAM chip is the IS61WV25616BLL-10TL from ISSI. These are 256K  x 16 so two would be required. Unfortunately the design of such a board is beyond our expertise so we'd be interested to know if anything already exists that could be used with the Mimas A7 Mini.

Nice project =) I talked about the Oberon system not long ago.

I understand the idea of using SRAM here, I think the original Oberon FPGA setup (from Wirth) was also using SRAM, but it'll take up a lot of IOs and I doubt you'll find a ready-made board for this. Of course, someone on here could design it for you. But the Mimas A7 dev board already has a 256MBytes of DDR3 memory - all you'd need it to implement a bridge between that and your CPU core. No hardware needed, only some HDL. And then a lot of RAM to play with.

[cfbsoftware]

But the Mimas A7 dev board already has a 256MBytes of DDR3 memory - all you'd need it to implement a bridge between that and your CPU core. No hardware needed, only some HDL.

Unfortunately, it is not quite as easy as it might sound. An implementation of Project Oberon Workstation on a Spartan-6 board does exist which uses LPDDR RAM. This involves more than 13,000+ lines of incomprehensible HDL just for the memory controller! This would be a maintenance and support nightmare. In contrast, the entire Project Oberon workstation is implemented in a total of only about 1300 lines of Verilog code with less than 50 lines needed for the SRAM controller. So unless somebody can come up with a significantly simpler, well-documented implementation of dynamic RAM it is just not an acceptable solution for us.

And then a lot of RAM to play with.

Project Oberon does NOT *need* a lot of RAM. It is not like a conventional operating system where every application has its own copy of library modules. Every module in the system is only ever loaded once in any session.  We have a version of the workstation running on an Artix-7 200T using as little as 500 KBytes of BRAM and no external RAM at all. 1 Mb is more than enough for most requirements. However, if more was required it can easily be doubled by using the 512K x 4 version of the ISSI SRAM chips with an extra address line as was done by Saanlima Electronics with their Pepino LX25 board.

[SiliconWizard]

Well, that was just a suggestion that sounded reasonable to me and probably to many users on this forum. We're actually talking about memory controllers quite often in here!

I understand SRAM is much easier to use. But I'm not sure I understand the implementation using LPDDR that you're talking about. Xilinx has memory controller generators that will get you a LPDDR or DDR3 controller with just a few clicks (I've actually used one on a Numato Saturn V3 board which happens to have LPDDR RAM), and those generated controller IPs are free to use. Of course you'd then need some interface between the CPU and this controller, but it certainly wouldn't require writing or maintaining thousands of lines of code, so I don't know exactly what they did here. Would you happen to have a link to this project, or is it closed source?

Of course one issue when a CPU is strictly written to access SRAM is that you might need to implement some cache if you want to port it to using DDR3, depending on bus frequency (because fully random accesses to DDR3 without cache is pretty slow). And for this, the CPU should also implement a way to wait for any memory access, which may not be implemented in this particular CPU and then I'll understand you don't want to mess with that.

But all in all, it certainly wouldn't take thousands of lines. Maybe those 13k lines you're taking about included Xilinx generated code, which would explain why it would look incomprehensible... but just realize it's generated by Xilinx tools and all you need is to learn how to use the controller's interface, which is documented.

Anyway, with that being said - so making sure you didn't miss on a possibility - if you really want a SRAM board with 1 MBytes of memory, it's going to be tough. I actually was looking for something like this a few years ago (between 1 MBytes and 2 Mbytes of fast SRAM on a small board to connect to some FPGA dev board), and never found anything off-the-shelf. You'll find some boards with SDRAM, some with PSRAM (but PSRAM would likely not fit the bill here either), but nothing with SRAM (or very small amounts of RAM.) Now if anyone knows of such a beast... Or, as I said, you could have it designed. Many people on here could design this for you, it looks like a pretty simple board to design. But it's probably going to cost something.

[cfbsoftware]

I understand SRAM is much easier to use. But I'm not sure I understand the implementation using LPDDR that you're talking about. Xilinx has memory controller generators that will get you a LPDDR or DDR3 controller with just a few clicks (I've actually used one on a Numato Saturn V3 board which happens to have LPDDR RAM), and those generated controller IPs are free to use. Of course you'd then need some interface between the CPU and this controller, but it certainly wouldn't require writing or maintaining thousands of lines of code, so I don't know exactly what they did here. Would you happen to have a link to this project, or is it closed source?

Thank you for your comprehensive reply. Yes - you are right - many of the lines were tool-generated. I have a long-standing aversion to source-generating 'wizards' but leaving that prejudice aside there are still 3 additional modules with more than 1000 lines and the top module was 3x larger than before. The code (for Saanlima's Pipistrello board) is on github:
https://github.com/Saanlima/Pipistrello/tree/master/Projects/Oberon_lpddr

Anyway, with that being said - so making sure you didn't miss on a possibility - if you really want a SRAM board with 1 MBytes of memory, it's going to be tough. I actually was looking for something like this a few years ago (between 1 MBytes and 2 Mbytes of fast SRAM on a small board to connect to some FPGA dev board), and never found anything off-the-shelf.

I didn't need such an add-on board at that time as suitable dev boards already equipped with enough SRAM existed. As well as Digilent's Spartan-3 I also have three boards with 1MByte of SRAM that were available off the shelf: the OberonStation, the Pipistrello with the Oberon wing, and Saanlima's other board, the Pepino LX9. I also bought a Pepino LX25 with 2 MByte SRAM. Not only is the Pepino great for Oberon I also use it as an Apple Mac Plus system. However, I now have a need for some more boards but none of these are available any more for sale.

Another option I have is to order the production of a batch of Pepinos myself as the hardware is now open source:
https://github.com/Saanlima/Pepino/tree/master/Board.
I have received a preliminary quote for the assembly of 10 boards which would be acceptable except that about a dozen of the components require substitution (including the SPI flash). Being a software person I'm reticent to mess around with alternative parts. Also, my first real preference (even more so than a Mimas mini with an SRAM daughterboard) would be an updated Pepino that used an Artix 7 rather than a Spartan 6. Vivado does not support Spartan 6 and I don't particularly want to go back to using ISE again.   

You'll find some boards with SDRAM, some with PSRAM (but PSRAM would likely not fit the bill here either), but nothing with SRAM (or very small amounts of RAM.) Now if anyone knows of such a beast... Or, as I said, you could have it designed. Many people on here could design this for you, it looks like a pretty simple board to design. But it's probably going to cost something.

Better than that, Magnus (the guy behind Saanlima) has designed a complete Oberon-capable board using an Artix 7 which he announced on the ETH Oberon mailing list. It is the closest to what I am looking for so far - apart from it using PSRAM. Yes - I know I am being fussy and I know it is going to cost something but I do have money to spend if the *right* system that I *want* appears. If nothing else better comes up in the next few months I might end up backing that horse.

[SiliconWizard]

I understand SRAM is much easier to use. But I'm not sure I understand the implementation using LPDDR that you're talking about. Xilinx has memory controller generators that will get you a LPDDR or DDR3 controller with just a few clicks (I've actually used one on a Numato Saturn V3 board which happens to have LPDDR RAM), and those generated controller IPs are free to use. Of course you'd then need some interface between the CPU and this controller, but it certainly wouldn't require writing or maintaining thousands of lines of code, so I don't know exactly what they did here. Would you happen to have a link to this project, or is it closed source?

Thank you for your comprehensive reply. Yes - you are right - many of the lines were tool-generated. I have a long-standing aversion to source-generating 'wizards' but leaving that prejudice aside there are still 3 additional modules with more than 1000 lines and the top module was 3x larger than before. The code (for Saanlima's Pipistrello board) is on github:
https://github.com/Saanlima/Pipistrello/tree/master/Projects/Oberon_lpddr

Thanks - I took a look. And this actually looks pretty reasonable to me. There's the code for the LPDDR memory controller, generated by Xilinx tools (you may not like auto-generated code but for such controllers you don't have much choice. Writing such a controller yourself IS hard. Note that someone on the forum is currently doing this, writing a DDR3 controller. But its not easy and I bet you may not uinderstand much better their code...) Then there is a source file for interfacing with the memory controller, and another one for implementing a memory cache, each about 600 lines of code. Not sure what the third is, but I'm not very familiar with the RISC5 CPU. But that's not a lot really. And since Xilinx controllers have the same interface, you could easily port this to another type of RAM, such as DDR3.

Thing is, between the Spartan-6 series and the 7-series, with Vivado, I think the interface for memory controllers has changed a bit? So there would be a bit of work there to port it to an Artix-7.

Now from what you said, I'm not entirely sure what your goal is in terms of hardware. Do you want to use an existing dev. board, as seemed to be the case, or do you want to design/have designed your own board?

There are very few FPGA dev boards with this amount of SRAM on the market. I do remember the boards you mention, but they are kind of old now, and anything based on a more recent FPGA (such as the 7 series) is likely to have some kind of DDR RAM and certainly not SRAM... Those Pepino boards are Spartan-6 based, and I don't know if they even are still available. But anything Spartan-3 based? That's much too old IMHO.

So I don't know what to suggest really apart from what I already said. Either have a board designed for your specs (for instance, with an Artix-7 and 1 MBytes of SRAM), have an extension board with SRAM designed for an existing board such as the MIMAS A7, or accept to use DDR3 RAM on it, but if it's a bit beyond your expertise or you definitely don't want to modify the original design in this way, then...

You mentioned a board from Magnus that would interest you except for PSRAM - which is an option I mentioned earlier, and would require modifications in the Verilog code too... and besides, you asked for 10 ns access time, this is not something you can get for random access through PSRAM. So you'd need to run your CPU at a rather low clock rate, or add some cache, something I guess you don't want to bother with either. But, if there is no board available with the specs you need, I don't really see an option apart from having it custom designed.