Author Topic: Open IP Example Design in Verilog?  (Read 1036 times)

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Offline notoothTopic starter

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Open IP Example Design in Verilog?
« on: May 11, 2024, 06:24:43 pm »
Hello everyone,
When I right click an IP in Vivado and choose 'Open IP Example Design', it creates a SystemVerilog module. How can I make it create a Verilog module?
 


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