Xilinx PLL Mamimum output frequency

[javad2040]

hello guys.
I design an FPGA board that contain Xilinx Spartan6 and Micron SDRAM. I wrote SDRAM Controller Code for transfer data. For testing the code i use Xilinx ChipScope. As i noticed the Chipscope  samples data on twice the Desing-under-test frequency; so i use Xilinx LogiCORE™ IP Clocking Wizard core for generate related clocks that the input clock is 18.432 MHz frequency and i need three Frequency that they are 92.16Mhz phase=0, 92.16Mhz phase=180 and 184.32Mhz phase=0.
When i select this frequencies in the clock wizard, the 184.32Mhz can't support and it is strange. can anybody help me to solve it?
 my purpose of 184.32MHz clock is to test my SD-RAM design with chipscope, which is not currently working

[dmills]

The problem is the PLL input frequency, see https://www.xilinx.com/support/documentation/data_sheets/ds162.pdf which give the PLL input minimum clock frequency as 19MHz.....

Can you replace the 18.432MHz osc with maybe one at twice that frequency which would then be easily within the PLL range?

Failing that, and with the proviso that you would be running the thing out of specification so it may or may not work, just lie! Tell the clock wizard that you are running with a 20MHz clock and tweak the output frequency settings to suit, odds are it will still lock. I would not do this in a production design, but if this is a one off prototype, then whatever works....

Regards, Dan.

[hamster_nz]

... however, if you use a DLL, the minimum input is 5MHz, so as log as you use the DLL you should be OK.

The DLL can only generate a single frequency, Maybe first use a DLL to generate the 184,32 MHz, then use a PLL after that to generate the clocks you really want.

[javad2040]

hi
thank you for reply.
fortunately my problem is solved. I use tow DCM for generate related clock signals that the first generates clocks with 92.16MHz and below frequency and second generates 184.32Mhz frequency.