Open source FPU with 1 cycle performance

[ali_asadzadeh]

Thanks brucehoult,

I've already pointed you to the source code for the Berkeley FPU (which you'd find somewhere inside that obfuscated E76 evaluation core).

Do you have any idea on How much resource and speed can it achieve on an ARTIX 7 device?

[brucehoult]

Thanks brucehoult,

I've already pointed you to the source code for the Berkeley FPU (which you'd find somewhere inside that obfuscated E76 evaluation core).

Do you have any idea on How much resource and speed can it achieve on an ARTIX 7 device?

You might find this paper interesting: https://hal.archives-ouvertes.fr/hal-02303453/document

They give figures for a number of RISC-V cores. For a Rocket implementing RV32IMF they get 76 MHz on an Artix 7 and 8132 LUT, 3094 FF. I'm pretty sure I've seen Rocket-based cores running at 100 MHz on an Artix 7 but that might be without FPU.

[ali_asadzadeh]

Does anybody know how to get verilog from the chisel?

https://github.com/ucb-bar/berkeley-hardfloat/

I want to generate verilog form this berkeley repo, there is also a build.sbt in the repo.

[ali_asadzadeh]

No Idea on how to compile chisel to Verilog, if anyone knows something please point it out for the berkeley-hardfloat on GitHub
So we can take a look at it, also I have found this useful open-source FPU, it's not what I wanted to accept data on every cycle, But it has low area and good speed, it can reach 150MHz on Gowin.

https://github.com/dawsonjon/fpu

[brucehoult]

No Idea on how to compile chisel to Verilog, if anyone knows something please point it out for the berkeley-hardfloat on GitHub
So we can take a look at it, also I have found this useful open-source FPU, it's not what I wanted to accept data on every cycle, But it has low area and good speed, it can reach 150MHz on Gowin.

https://github.com/dawsonjon/fpu

You generate Verilog from chisel by ... running chisel. That's its purpose.

Well, these days chisel itself generates FIRRTL (Flexible Intermediate Representation for RTL), and then you run various optimizations on the FIRRTL (including such things as optimizing for SoC or for FPGA, and then you convert the FIRRTL to Verilog or I think VHDL is also an option.

You can also I believe convert Verilog or VHDL to FIRRTL for optimization.

[ali_asadzadeh]

Thanks bruce, do you recommend any  tutorials on chisel?

[brucehoult]

Thanks bruce, do you recommend any  tutorials on chisel?

I used to work with the people who made it (and continue to enhance it) but I've never used it myself.

A quick  google search finds tutorials at Berkeley University, and this one seems reasonable as a quick start:

https://www.instructables.com/Getting-Started-With-Chisel/

But I just found that in 30 seconds so I expect you've already looked at that and more in the last five months since your initial messages.