Open Source Verilog Package Manager

[spec_superior]

I'm a Stanford student who previously designed ASICs at a startup and also dabbled in FPGAs.

I built a Verilog Package Manager to address some issues with IP re-use. It's basically the equivalent of pip install, because installing a top-level module automatically installs submodules, handles synthesis collateral, generates .vh headers, etc.

Within 2 days of launch it received interest and feature requests from Neuralink and Samba Nova engineers. I'm trying to make this big but practical.
Repo link: https://github.com/getinstachip/vpm

I'd appreciate any comments or complaints on this. I'll fix each issue with a few hours. Looking for genuinely candid feedback and potential contributors. I'll answer any questions you have below too. I'll add people who are interested to a Discord server.

[zapta]

Have you considered to support a central repository similar to PyPi.org?