Electronics > FPGA

OpenHBMC. Open-source AXI4-based HyperBus memory controller

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--- Quote from: kmike on December 17, 2020, 02:51:39 pm ---Thanks!

Great work!

Ramtest usin Microblaze passed on a Trenz 0725 Board (Artix7 + 64MBit HyperRam) @ 100MHz! Update: Test also passed at 166MHz

--- End quote ---
Hi, kmike , thanks for feedback, glad to hear that. BTW, I'm not completely sure, but rwds signal position is critical. As rwds is used as a clock signal, it should be connected to clock capable pin of the bank, i.e. SRCC or MRCC. I have two boards with Spartan-7 XC7S100 and XC7S50. On the first board with XC7S100 the rwds is connected to the SRCC and I also could pass memtest at 162MHz. But at the second board with XC7S50 the rwds is not at clock capable pin and I can't meet timings at frequencies >125MHz.

Nevertheless, I would like to run this memory controller at maximum speed that memory part supports (for my W956D8MBYA5I the limit is 200MHz) with slowest 7-series FPGA, i.e. Spartan-7 family with -1 speedgrade. I have an idea of completely another way of incomming data capturing over ISERDESE2 in OVERSAMPLE mode.
Yes, this is a bit more complex, but for my opinion this solution is going to be much faster, more reliable and probably there will be no need to make calibrations or even use idelay primitives. Details further...


on the Trenz board the RWDS signal ist not connected to a CC pin, but still happily passes ramtest @ 166MHz. I can not increase the frequency, because the RAM chip (S27KS0641) on this board is not capable of 200MHz. The FPGA is an Artix-7 35t -2 speed grade.

I will use the memory at 100MHz for this project (camera to TFT adapter), because my pixel clock is only 5MHz  :)


Hello everyone!

Some updates. New HyperRAM controller version. Achieved 200MHz clock speed on Spartan-7 (-1 speed grade) with W956D8MBYA5I part.
Repo: https://github.com/OVGN/OpenHBMC

Hello, can your hardware board be sold? I want to buy a set of boards。

Well done. compatibility can be an issue , not all HyperRAMs are created equal.


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