Electronics > FPGA

Or-ing std_logic_vector of dynamic sizes

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polarKaung:
Hello, a question.

How do I "or" two std_logic_vector of different sizes? Is that even possible?

for example:
signal a : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
signal c : std_logic_vector(7 downto 0);

c <= a or b(index downto 0); -- where index is within 7 and 0 and comes from somewhere in the design) ^-^

Daixiwen:
What exactly are you trying to do? Do I understand correctly that your c and a vectors are still 8 bits wide, but that you want to combine a with only a variable number of least significant bits in b?
The or operator itself requires the two vectors to be of the same size. You can build an "extended" version of b always 8 bits wide, in which only the least significant bits that you want are copied from b, and the other most significant bits just set to 0. Then combine this vector with a to build c:
--- Code: ---b_ext <= (index downto 0 => b(index downto 0), others => '0');
c <= a or b_ext;
--- End code ---
This code should work in a simulator, but some synthesizers won't like the variable length. In that case you will need to create a for loop instead and just operate on each bit individually. Something like that (not tested/compiled)
--- Code: ---or_operation: for i in 7 downto 0 generate
  if i <= index then
    c(i) <= a(i) or b(i);
  else
    c(i) <= a(i);
  end if;
end generate;
--- End code ---
Alternatively if you can make your vectors of the signed or unsigned type instead of std_logic_vector, there is a resize() function that you can use directly.

rstofer:
I don't like the clever solutions because I can't convince myself that they will actually work.  I would spend a lot of time looking at the RTL Schematic to understand what was generated.

Instead, I would generate all 8 conceivable vectors and use a MUX to select the version I want.  Maybe a 'conditional assignment' would provide clarity.

https://www.ics.uci.edu/~jmoorkan/vhdlref/cond_s_a.html

polarKaung:

--- Quote from: Daixiwen on November 29, 2021, 02:38:14 pm ---What exactly are you trying to do? Do I understand correctly that your c and a vectors are still 8 bits wide, but that you want to combine a with only a variable number of least significant bits in b?

--- End quote ---

yes the c and a vectors will still be 8 bits wide.

what i want is like
lets say index = 5
then
c <= a or "00" & b(index downto 0);

if index = 2
then
c <= a or "00000" & b(index downto 0);

SiliconWizard:
Various ways of doing this of course.

Apart from what Daixiwen suggested, here is one of them guaranteed to synthesize and not overly convoluted:


--- Code: ---c(c'high downto index + 1) <= a(a'high downto index + 1);
c(index downto 0) <= a(index downto 0) or b(index downto 0);
--- End code ---


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