Have anyone used OSERSEDESE2 with CLK and CLKDIV not phase aligned? I am confused by the UG471 documentation, page 161 says "The OSERDESE2 uses two clocks, CLK and CLKDIV, for data rate conversion. CLK is the
high-speed serial clock, CLKDIV is the divided parallel clock. CLK and CLKDIV must be
phase aligned." But in figure 3-11 at page 169 "Note: In Table 3-11, the CLK and CLKDIV clock edges are normally not phase aligned"