Author Topic: OSERDESE2 CLK and CLKDIV phase relation  (Read 1784 times)

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Offline ddr_controllerTopic starter

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OSERDESE2 CLK and CLKDIV phase relation
« on: March 03, 2023, 03:46:39 pm »
Have anyone used OSERSEDESE2 with CLK and CLKDIV not phase aligned? I am confused by the UG471 documentation, page 161 says "The OSERDESE2 uses two clocks, CLK and CLKDIV, for data rate conversion. CLK is the
high-speed serial clock, CLKDIV is the divided parallel clock. CLK and CLKDIV must be
phase aligned
." But in figure 3-11 at page 169 "Note: In Table 3-11, the CLK and CLKDIV clock edges are normally not phase aligned"
 

Offline hamster_nz

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Re: OSERDESE2 CLK and CLKDIV phase relation
« Reply #1 on: March 07, 2023, 08:03:13 pm »
In the clocking section of that user guide it states:
Quote
The phase relationship of CLK and CLKDIV is important in the serial-to-parallel
conversion process. CLK and CLKDIV are (ideally) phase-aligned within a tolerance.

Table 3-11 is a table of latencies through the SERDES block.

Quote
Latency is defined as a period of time between the following
two events: (a) when the rising edge of CLKDIV clocks the data at inputs D1–D8 into the
OSERDESE2, and (b) when the first bit of the serial stream appears at OQ

I read note at the bottom of the table as saying "in some cases, when CLK and CLKDIV are aligned to within the jitter of both clocks, the calculated latency can vary by one cycle".

The alignment required to have this difference in latency occur is smaller than the phase alignment required between CLK and CLKDIV.

I'm guessing somebody measured the latency in simulation and it was off by one cycle.
« Last Edit: March 07, 2023, 09:05:44 pm by hamster_nz »
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Offline SiliconWizard

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Re: OSERDESE2 CLK and CLKDIV phase relation
« Reply #2 on: March 07, 2023, 08:08:01 pm »
OSERDESE2 is for the 7 series if I'm not mistaken? Haven't used OSERDESE2 yet on Artix-7, but I've used OSERDES2 on Spartan-6, and CLKDIV for it required to be phase-aligned with the serial clock, usually generated using a PLL_ADV, dividing the serial clock by N.
 


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