Author Topic: Need decode the 8B10B data sequence of 1.3Gbps speed within Lattice FPGA LFE-5UM  (Read 2135 times)

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Offline namyelusTopic starter

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  • Country: th
Hello All Community,

I'm currently working on a project involving decoding UFS (Universal Flash Storage) output signals using an FPGA. My setup includes an oscilloscope to monitor the UFS input/output signals and the FPGA's decoded output. I've encountered an issue where error bits are present in the FPGA's decoded output. The oscilloscope waveform reveals that the FPGA's signal processing speed is not reaching the required 1.3Gbps.

To address this, I've made software and firmware updates but have not replaced the FPGA hardware. During testing, I discovered a potential solution: synchronizing the FPGA's PLL (Phase-Locked Loop) output with the UFS input/output frequency might resolve the issue.

The PLL output frequency is largely influenced by its source signal. Currently, there are two clock signals on the FPGA board (200MHz and 52MHz), which I plan to replace. My next step is to calculate a suitable operating frequency and order a new crystal oscillator accordingly.

After replacing the crystal, I aim to complete the UFS input/output in High-Speed (HS) mode within one week..

Here's where I need your expertise:

How can I best synchronize the FPGA's PLL output with the UFS input/output frequency to reach the desired 1.3Gbps?
What considerations should I take into account when calculating the new operating frequency for the PLL?
Are there any potential pitfalls or common mistakes I should be aware of when replacing the crystal oscillator on the FPGA board?
Any insights or suggestions from the community would be greatly appreciated!

Thank you in advance for your help!

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