EEVblog Electronics Community Forum
A Free & Open Forum For Electronics Enthusiasts & Professionals
Welcome,
Guest
. Please
login
or
register
.
Did you miss your
activation email
?
1 Hour
1 Day
1 Week
1 Month
Forever
Login with username, password and session length
This topic
This board
Entire forum
Google
Bing
Home
Help
Search
About us
Links
Login
Register
EEVblog Electronics Community Forum
»
Electronics
»
FPGA
»
PALCE programming algorithm
« previous
next »
Print
Search
Pages: [
1
]
Go Down
Author
Topic: PALCE programming algorithm (Read 2579 times)
0 Members and 1 Guest are viewing this topic.
TomS_
Frequent Contributor
Posts: 851
Country:
PALCE programming algorithm
«
on:
March 09, 2022, 02:52:26 pm »
Hi all,
Would anyone happen to know whether PALCE devices use the same programming algorithm as GAL devices, or if they are completely different?
Thanks
Logged
Beta_vulgaris
Regular Contributor
Posts: 71
Country:
Re: PALCE programming algorithm
«
Reply #1 on:
March 10, 2022, 10:41:01 am »
With some similarities, all of them require high voltage ("programming voltage") on one or more of input-only pins. But the detailed algorithm may be completely different. Here are GAL22V10 (EEPROM) and PALC22V10 (UV EPROM) diagrams:
Logged
Electronics, Geospatial, Aerospace
Programmable Logic Devices (PLD) Programming Algorithm Preservation
Print
Search
Pages: [
1
]
Go Up
« previous
next »
Share me
Smf
EEVblog Electronics Community Forum
»
Electronics
»
FPGA
»
PALCE programming algorithm
There was an error while thanking
Thanking...
EEVblog Main Site
EEVblog on Youtube
EEVblog on Twitter
EEVblog on Facebook
EEVblog on Odysee