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Electronics => FPGA => Topic started by: davorin on October 18, 2021, 02:58:04 pm

Title: PDM Verilog demodulator
Post by: davorin on October 18, 2021, 02:58:04 pm
Good afternoon (o;

For a project I would like to use some PDM microphones as they are better available than I2S ones....and I already have them (o;

Googled around today how the conversion from PDM to PCM could be done for further processing in FPGA....and all papers talk about decimation with filtering...
but I couldn't find any reference to any actual implementation in Verilog....and the FPGA IDE tools I want to use (Efinix and Gowin) don't come with decimation soft IP.

Or could the decimation just be done like dping a rolling average on a constant amount of bits read in?


thanks in advance from a total signal processing noob (o;
richard
Title: Re: PDM Verilog demodulator
Post by: Someone on October 19, 2021, 02:06:53 am
Or could the decimation just be done like dping a rolling average on a constant amount of bits read in?
Yes, that works, but may have more noise and poorer frequency response than more sophisticated methods.
Title: Re: PDM Verilog demodulator
Post by: dawnclaude on October 19, 2021, 07:15:06 am
Here is a useful blog series that explain how to choose filter parameters depending on the mic specifications and your needs:
https://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.html (https://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.html)
In the design above there is a CIC and cascaded half band filters that gradually reduce the sampling rate which lets you do the filtering in less number of multiply and accumulate operations compared to using a single sharp lowpass filter.

That said, on FPGA, I just use a single lowpass filter with a very sharp transition. Numbers will depend on the implementation, type of FPGA resources and vendor tools but in my case:

A FIR lowpass filter with 3500 taps with transition from 12kHz to 16kHz, passband ripple of 0.1 dB and stopband attenuation of 120 dB
Input sampling rate and PDM clock frequency 3.125 MHz
You just downsample the filter output by 96 to end up with 32.55kHz sample rate with minimal aliasing

Final resources:
2 DSPs
3.5 BRAMs

I have used the Xilinx FIR Compiler to implement the filter since I have a 7-series FPGA. Not sure if GOWIN will produce a design as optimzed as this if it has a FIR tool. Of course you could implement the filter yourself with HDL  :-//
You can calculate the filter coefficients using your favourite math tool.
Cheers.