Pin assignment in SoC

[moonz]

Hello everyone, I study circuit SoC (for example Cyclone V).
I'm a little confused about the pin assignment. Let's take a IC Cyclone V 5CSEBA2(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/5cseba2.pdf) for example.
Do I understand correctly, that the HPS pin are indicated in the columns HPS Pin Mux Select 0..4, only owned by HPS? Or can they also be attributed to FPGA functions?

I also want to clarify, I understand correctly that the DDR memory controller for HPC and FPGA is common and, as a result, the pin are also common. Is this a correct statement?

Can you please tell me what is the purpose of the column for VREF?

Thanks in advance!

[ejeffrey]

Yes, the HPS pins are owned by the HPS and cannot be directly accessed by the FPGA fabric.  The FPGA pins likewise are only accessible from FPGA fabric.  You can really think of the whole system as two completely separate devices on the same die connected by an AXI bus.  You can boot the HPS prior to loading a configuration bitstream onto the FPGA (which allows you to have the HPS program the image) or you can configure the FPGA before providing a boot image for the HPS (which allows the HPS to boot from an IO device present in the FPGA).

I believe the model you are looking at does not have a hard memory controller in the FPGA fabric.  The only memory controller is attached to the HPS and has dedicated pins reserved for it.  You can tell by the 'B' in the part number that would be an 'F' if it has hard memory and PCIe controllers.  So the FPGA cannot directly access DRAM.

[moonz]

So the FPGA cannot directly access DRAM.

FPGA has no direct memory access? I ask because I see figure 11 in the document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51001.pdf

Refre by this diagram, both the FPGA and the processor have access to memory. Or are there mistakes in my reasoning?

[Daixiwen]

You are right, the FPGA fabric can directly access the SDRAM connected to the HPS SDRAM controller, through the FPGA-to-HPS-SDRAM interface. It can also use the FPGA-to-HPS memory mapped interface (on the left) to access any address in the HPS space, including peripherals and RAM.
Some HPS pins can be accessed from the FPGA fabric, but their number is limited (32 total I think?) and don't expect high I/O timing performance from them. When you configure the HPS core in QSys, you can connect each HPS pin either to a hardware I/O controller inside the HPS (uart, spi, ethernet....), as a GPIO, or as connected to the FPGA fabric. In the latter case QSys will export a logic vector for you to use.