Electronics > FPGA

Planning/design/review for a 6-layer Xilinx Artix-7 board for DIY computer.

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asmi:

--- Quote from: Gribo on July 25, 2023, 01:16:30 pm ---The capacitors for the ethernet XTAL are a bit off. 20pF CL crystal requires ~27pF for each the capacitors - they are in series and 0402 has ~1pF parasitic capacitance per pad.

--- End quote ---
Thank you, I've updated schematics (also changed load caps for FT2232 as well). There were also some other changes as well.

Gribo:
Can you post new pictures? You have changed some reference designators and it is a bit confusing (J9). I would make all the expansion connectors safely interchangeable, that is, if something is connected to one, it can be safely connected to the others. It might not work, but it shouldn't short out or cause damage.

asmi:

--- Quote from: Gribo on July 25, 2023, 05:18:12 pm ---Can you post new pictures? You have changed some reference designators and it is a bit confusing (J9).

--- End quote ---
Attached. I've added some more connectors and jumper-selectors (for example for M[2] ball so that FPGA can be set up to boot from QSPI, or not boot at all expecting to be configured via JTAG). Also I forgot to add package pin delays during initial layout, now I've added it and fixed delay matching so that those delays are taken into account.


--- Quote from: Gribo on July 25, 2023, 05:18:12 pm ---I would make all the expansion connectors safely interchangeable, that is, if something is connected to one, it can be safely connected to the others. It might not work, but it shouldn't short out or cause damage.
--- End quote ---
I use the same connector for MGT expansion connector and for a one with differential pairs, pinout is designed to be "compatible" in a sense that nothing should blow up if you connect it to the wrong position - power and ground pins are in the same positions (or not connect), but of course depending on what VADJ1/VADJ2 are set to, circuitly on a daughterboard might not like it if it's set to anything other than what it expects, so I do expect some level of diligence on the part of a user.
Third expansion port (Port 2) is using a different connector, so it's not possible to connect it anywhere else.

asmi:
I've finally managed to get enough spare time to assemble and thoroughly test the board, and as usual for me, I got quite a few things wrong ::) So here it is, the good, the bad and the ugly:
1. I had the wrong pinout for LVDS clock generator. Managed to fix it by shifting the generator one pad to it's side and adding a couple of bodge wires. Will be fixed for rev B1.
2. I messes up the pin numbering for a voltage translator (numbering begins in the middle of one of sides, and not from one side as usual). As a result, this revision is unable to use QSPI flash memory at all. Thought about bodging, but decided that it's going to be too much trouble. Footprint will be fixed for B1, but I still can't know for sure if it's going to be functional. Will see.
3. Had lots of troubles getting MPM3632C's to work. Turned out to be bad soldering, once I added some solder to the sides, they started working. Very finicky stuff. I've extended the pads somewhat to allow for more solder, will give it another go in B1, if it will still prove to be troublesome, will consider replacing them with regular DC-DC converters, which worked perfectly right from the get-go.
4. I soldered the crystal for Ethernet PHY turned at 90° to what it should be (assembly error), once fixed, it started working with no issues. Confirmed full functionality via hardware evaluation version of Xilinx TriMAC IP (and some mild tweaking of the lwip code to get PHY configured properly). Also tried it with some homemade MAC, and it seems to work just fine.
5. DDR3 SODIMM worked right from the get go with 8GByte module from Micron. I want to buy some more DDR3 SODIMMs from random vendors just to see what it takes to get MIG to work with various off-the-shelf modules found for pennies in computer stores, as "brand" Micron stuff is very hard to find in stock anywhere. That was the biggest design risk, so I'm super happy that it worked right off the bat  :-+
6. HDMI out gave me some grief, but the problem turned out to be a bad HDMI cable |O Once replaced, everything started working smoothly, but I still wasted almost entire day before I decided to test with a different cable. I also forgot to include pullup resistors on the FPGA side of things (after redriver IC) for DDC, and mixed up SDA/SCL lines, fixed that for B1.
7. I was unable to test fan as dummy me bought the wrong fan (5 V instead of 12 V) :palm:. But I can't really see how it can be screwed up.
8. I wired thermal alarm signals to be on-high while the actual signals are on-low :palm: So I have two more LEDs permanently on than I intended to. Fixed for B1.
9. This is just a nitpick, but my user switch goes to high when moved down, which bothers my OCD. Turned it around for B1.
10. All other user IOs (RGB LEDs, regular LEDs, pushbuttons) work like sharm. No real suprises here.
11. FT2232-based JTAG programmed also just worked right after programming. But I was fairly sure it will after I had prototyped this subcircuit on a dedicated PCB. One minor nitpick is that TX/RX directions in FT2232 datasheet are from the USB's point of view, so I had my silkscreen wrong. Fixed for B1.
12. I realized that a cooling fan would be really useful as FPGA die temp reached 75°C in some cases once you really load it up. I have an "I"-rated FPGA, so it's good to 100°C, but I don't like that it's so hot.

And two more things I learnt during assembling of this board: 1 - QFNs on the bottom side are just fine and they stay put after reflow of the top side :-+ I always suspected that would be the case, but it's good to have practical confirmation. and 2 - via in a pad technology rocks :-+ as it allowed me to avoid using 0201 caps and use 0402's instead, which helped massively during assembly.

Attached is a high-ish resolution photo of the top side as it looks right now, you can see some bodges, resistors attached to vias, and a lot of residue from soldering. I'm frankly afraid to subject the board to an ultrasonic wash as I'm afraid it's going to tear some of my bodges away.

I'm currently putting some finishing touches on a rev B1, as I made some more minor changes and additions, will post it here once it's ready.

asmi:
Second revision is assembled and fully tested. There is a minor mistake in schematics (which appeared in this revision as it didn't exist in previous one), but nothing that can't be fixed with a couple of bodges. I've added a Microchip's EEPROM with pre-programmed MAC address (PN: 24AA025E48T-I/SN) to use when implementing Ethernet, since I didn't have any free IO pins, I've connected it to two lines which lead to SMA connectors with a pair of zero Ohm resistors so that they can be removed if neccessary, I've also connected SODIMM's SPD bus and thermal sensor's I2C bus to these lines as well (again with jumper resistors).

Attached are full schematics in case anyone is curious, as well as a photo of the assembled board. Unfortunately I couldn't find any heatsink with fan which is small enough for 23x23 mm package, so I had to improvise :-/O This heatsink is actually 27x27 mm, and I have an idea to buy smaller version of it and make a couple of holes with M3 thread, so that I can mount a fan that way. I will need to do some experiments later.

As you can see on the photo, regular COTS SODIMM module works just fine, so no need to hunt after rare Micron modules, which are the only ones supported officially, but since any SODIMM DDR3 is required to work at JEDEC timings, there shouldn't be any problems using any random module you happen to have on hand. I'm planning to buy a couple more of COTS SODIMMs in the near future to confirm this theory (since they are so cheap, it shouldn't really be a problem).

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