Playing with old XC3000A + XACT 5.2.1... no pins assigned or routed

[ZaneKaminski]

Any Xilinx users from back in the day who can give me some advice?

I’m playing with old Xilinx stuff and can’t quite get a design going in XACT. I’ve got a simple example in ABEL from Xilinx. It’s a 3-bit, 7-state counter which is decoded into seven one-hot outputs. (Source attached; it’s basically straight from Xilinx)

During synthesis, the XNFPREP logic optimizer ends up trimming all the logic in the design under the impression that the clock signal is sourceless. The apparent solution for this was to use the -savesig option: "don't trim sourceless or loadless signals.” Then the design maps and P&Rs with apparent success, but then the same issue is manifest in the routed FPGA. The logic is in there but there are no connections to the IO blocks. (see attached picture)

I was under the impression that if I didn’t make any pin assignments, the fitter would choose for me like in new tools. Is that not correct? Do I need some kind of top-level entity other than the ABEL file? Pin constraints file? I’m lost with these old tools lol… Also, any signal named “A” is always totally removed somewhere in the process. I changed it to “OUTA” and it didn’t get deleted. I guess it’s some kind of reserved identifier somewhere. But that’s not the main issue.

Anyone know what I’m doing wrong here?

[pcprogrammer]

I never used XACT 5, but do remember from when I used earlier versions of XACT, I had to map the logic to the pins, or at least that is what I did.

Used to use Orcad for schematic entry and use the IPAD, OPAD and BPAD primitives to make the connections.

Can't remember if there was an option to have the software make "random" connections for you.

[miken]

My experience only goes back to XC9500XL but yeah CPLD tools are way less smart than FPGA tools.

[ZaneKaminski]

I never used XACT 5, but do remember from when I used earlier versions of XACT, I had to map the logic to the pins, or at least that is what I did.

Used to use Orcad for schematic entry and use the IPAD, OPAD and BPAD primitives to make the connections.

Yes! Thank you! Well I don't have Orcad, just XACT. But it was easy enough to figure out the text-based XNF netlist format and write my own top-level entity which wraps the netlist generated from the ABEL source. Works great!

For anyone else with this issue, unlike the screenshots of Orcad I've seen, you don't need to instantiate the "PAD" entities. What's important is the "BUF" entities. IBUF, OBUF, etc. I was busy combing the internet for XNF files trying to figure out the library names for some of the more unusual input circuits, for example the INLAT input latch. I had resorted to disassembling the Xilinx programs looking for the various strings--success assured but very tedious-when I came across the whole XNF spec online: http://ebook.pldworld.com/_semiconductors/Xilinx/AppLINX%20CD-ROM/Rev.7%20(Q3-1998)/docs/wcd00016/wcd01660.pdf (file also attached so the info doesn't get lost) Fantastic! I'm used to new stuff where the vendors never wanna publicly disclose the specifics of their various formats. This spec came right on the Xilinx CD.

[Beta_vulgaris]

I have tested the example designs of various XACT versions with WorkView.

[ZaneKaminski]

I have tested the example designs of various XACT versions with WorkView.

And thank you for preserving all of those old versions of XACT, MAX+PLUS, etc! Beyond schematic capture being a kind of outdated design entry method, I had two issues with Workview. Firstly I’m (for better or worse) using Dosbox on an ARM MacBook. Dosbox doesn’t play nicely with Workview. QEMU world probably work but there’s some bug where IDE CD-ROMs don’t work in DOS. So I’m using Dosbox.

One thing I noticed about your XACT and XACTstep images is that the cracks included don’t work on all the XACT executable files in the image. Slightly different versions? Their checksums must differ from the version the crack is for. I contacted Xilinx support and they gave me another XACT 5.2.1 + XACTstep 6 image with slightly different executables. This also came with the same xpatch12 crack and it worked on the files in the image from Xilinx.

Any thoughts about this? I can upload the image I got from Xilinx too.

[Beta_vulgaris]

I have tested the example designs of various XACT versions with WorkView.

And thank you for preserving all of those old versions of XACT, MAX+PLUS, etc! Beyond schematic capture being a kind of outdated design entry method, I had two issues with Workview. Firstly I’m (for better or worse) using Dosbox on an ARM MacBook. Dosbox doesn’t play nicely with Workview. QEMU world probably work but there’s some bug where IDE CD-ROMs don’t work in DOS. So I’m using Dosbox.

One thing I noticed about your XACT and XACTstep images is that the cracks included don’t work on all the XACT executable files in the image. Slightly different versions? Their checksums must differ from the version the crack is for. I contacted Xilinx support and they gave me another XACT 5.2.1 + XACTstep 6 image with slightly different executables. This also came with the same xpatch12 crack and it worked on the files in the image from Xilinx.

Any thoughts about this? I can upload the image I got from Xilinx too.

They have been patched already as the file modified time imposes.