PLLs or otherwise clock management blocks with clock enables

[SiliconWizard]

So, as the title suggests, does anyone here have successful experience using clock enables in PLLs (or other clock management blocks)? Any advice? Also, if you have, what was the reason? Have you ever done this for power consumption reasons?

By clock enable, I mean a digital input in, for instance, PLLs, that allow "switching off/on" the clock output in a glitch-less way. ECP5 FPGAs, for instance, that I'm currently working with, have this feature, and I'm considering using this to lower power consumption when some parts of the design can be halted (like, say, a CPU core.)

Doing this purely on a HDL level as "clock gating" most often doesn't give you the expected result on FPGAs, which is why I'm considering clock enables in clock management blocks that can actually drive proper clock routing resources. In this case, disabling a clock output should completely stop any switching of any FPGA resource clocked by it...

[NorthGuy]

I don't know ECP5.

Most likely the PLL will have some sort of EN or RESET pin. However, when PLL starts the clock may not be stable right away. Xilinx has the LOCK pin which goes high when the clock become stable. Therefore, they recommend switching the clock off until LOCK is high. I've never tried to figure out what really happens before LOCK goes high.

Xilinx also have various clock buffers which can be switched on and off glitch-free - BUFGCE, BUFHCE, BUFRCE, which can be used to disable clocks to various logic areas. These are probably better than killing PLL.

[Someone]

Xilinx has the LOCK pin which goes high when the clock become stable. Therefore, they recommend switching the clock off until LOCK is high. I've never tried to figure out what really happens before LOCK goes high.

Xilinx also have various clock buffers which can be switched on and off glitch-free - BUFGCE, BUFHCE, BUFRCE, which can be used to disable clocks to various logic areas. These are probably better than killing PLL.

The hint is that they offer glitch free gating/muxing as separate parts. When the (Xilinx) PLLs arent locked you can end up with pulse widths and periods otherwise violating the timing... that can lead to "interesting" side effects.

[SiliconWizard]

Yep. As I thought was clear from my post, I'm strictly talking about glitchless enabling of clocks.

I mentioned PLLs because Lattice parts happen to have PLL blocks which include glitchess clock enables; Lattice calls that "dynamic clock enable". They do not stop the PLL but just act on the clock output. Now as I said with "other clock management blocks", it could of course apply to any other kind of clock management resource. It is clear that I didn't intend to stop PLLs. This wouldn't be glitchless and would make, unless done with additional measures, "halting" and "resuming" processes fully unreliable.

Also, unless the FPGA is very small and very low power, and/or clocked at a very low frequency, stopping a PLL would probably cut a small fraction of the power consumption compared to what you can save by disabling the clock for most of the internal logic you're using while the PLL itself (if you use one) is still running.

I've never used the clock enables of clock buffers on Xilinx parts, but it looks like it would do the job as well, and I suppose cascading a PLL and a clock buffer would achieve the same thing as what you can do with Lattice's PLLs, unless there are some routing restrictions for Xilinx clock buffers that I'm not familiar with.