Pls suggest small cheap FPGA with 3Gbps tranceivers

[asmi]

I am not confident with my non-existent BGA skills. As I'll get confidence in soldering these bad boys, I may as well opt for a $70 chip, because its price gets dissolved in the rest quite easily, but not if you kill two of these in a row (reading everywhere now and then how the BGA is sensitive to this or that...).

I said here like a million times already - if you want to get BGA soldering practice on cheap, buy some super cheap QSPI flash in BGA24 package, design a small breakout and go crazy! It's easy to break out on just 2 layers, it's trivial to connect it to any MCU you've got around with SPI bus to verify if soldering went well, and it's the cheapest part I know of which is 1)BGA, and 2)you can easily verify soldering.

You may (or not) understand, that after learning some basics in vendor's A toolbox I don't want to start over again with vendor B or even D.

No, not only I don't understand, but I actively disagree with this approach because knowing multiple vendors' tools not only gives you more options, but it also broadens your perspective as something different vendors solve the same problem differently, and it's helpful to know ups and downs of each one.

I may sound at times as if I actively hate Altera/Intel (I like to call them Antel for short ), but I actually don't. Their FPGA board and toolchain have been my very first ticket into the world of FPGAs, and I'm thankful to them for what I've learnt, how to do some things, and how NOT to do them So by the time I moved to using Xilinx devices, I already had some knowledge and experience, and that might explain in part why working with their devices seems much easier to me. I also used some Lattice devices - mostly to just get to know them a bit better than one can do by just reading a datasheet.

So having more-or-less working experience with multiple vendors' tools is a big asset, and never a liability.

[Yansi]

I have some NOR FLASH memories in BGA64x1mm packages ready, that may serve the purpose, but soldering a miniature BGA does not equal soldering a BGA256/324/484. Applying even heat will be more difficult. That's why I'm afraid of higher failure rate, than with soldering the small one. But I may be successful, who knows... time will tell.

I kind of understand why knowing more vendor toolboxes is beneficial - unfortunately in my case, it would mean I would have two (even three), but neither one nor the other would I know enough to be able to do anything properly. Look, I haven't still even figure out how to write a freaking testbench in the Quartus, let alone constraint the design properly (declaring clock period doesn't cut the mustard I guess..)

In the end I would really love to know all three major ones, but now I'm glad I can do at least something basic in one of them.

And yes, I am very pesimistic, paranoid or whatever. I know myself long enough to know I always screw up badly.

[Someone]

So hobbyist shall only use an off-the shelf module according to your consistent logic?

Its the cheapest way to achieve what you want, unless you value our time and yours as $0. Fine pitch BGA is not something that is cheap in low quantity, but you want to try it anyway for some (unspecified) reason.

There is no defeat in using modules, they take all the "hard" bits out of the design as someone has already done the work/manufacturing.

If you roll your own board from scratch I'd be predicting a few threads about how to design the power systems, and route the high speed traces. If you want to learn that stuff go ahead, but stop complaining that its expensive as the parts are a tiny cost compared to the engineering effort.

[BrianHG]

This is the cheapest 484pin 1mm bga with transceivers:
https://lcsc.com/product-detail/CPLD-FPGA_Altera-EP4CGX50CF23C8N_C568986.html
Though, it is way too large for your app if the EP4CGX15 was on your hit-list.

[asmi]

Look, I haven't still even figure out how to write a freaking testbench in the Quartus

This specific function is implemented way better in Vivado, because it's got a fully featured integrated simulator, as opposed to a bolted-on external one crippled to death in order to entice you to buy a license for a less-crippled version. So adding a testbench in Vivado is just a matter of adding a simulation-only module without ports, IDE will automatically recognize it, and all that will be left to do is to click "Run Simulation" button.

[Yansi]

This is the cheapest 484pin 1mm bga with transceivers:
https://lcsc.com/product-detail/CPLD-FPGA_Altera-EP4CGX50CF23C8N_C568986.html
Though, it is way too large for your app if the EP4CGX15 was on your hit-list.

Great find! However currently zero stock. Hopefully one day I'd be able to use all the balls. 

EP4CGX15 fulfills all needs, apart that the transceivers are 2.5Gb. But I can live with that, at least for now - as a training to layout the BGA. Then will need to find a faster device anyway.

Look, I haven't still even figure out how to write a freaking testbench in the Quartus

This specific function is implemented way better in Vivado, because it's got fully featured integrated simulator, as opposed to bolted-on external one crippled to death in order to entice you to buy a license for less-crippled version. So adding a testbench in Vivado is just a matter of adding a simulation-only module without ports, IDE will automatically recognize it, and all that will be left to do is to click "Run Simulation" button.

I remember even in ISE there was just a switch either simulation or synthesis+P&R. 
I have installed some Modelsim something in Quartus, but never got it to fully work as I expected it to.

[BrianHG]

> 3gb for $15.77 : https://lcsc.com/product-detail/CPLD-FPGA_XILINX_XC7A35T-2FTG256C_XC7A35T-2FTG256C_C181716.html

I think this one is 6gb/sec...
And there is stock.

You no longer have any complaints.
Also, JLPCB will mount the FPGA since their SMD assembly service for their PCBs get their components from LCSC.

Ooops, Xilinx did a dirty move...

[asmi]

> 3gb for $15.77 : https://lcsc.com/product-detail/CPLD-FPGA_XILINX_XC7A35T-2FTG256C_XC7A35T-2FTG256C_C181716.html

I think this one is 6gb/sec...
And there is stock.

Unfortunately this package does not bond out any transceivers.

[BrianHG]

> 3gb for $15.77 : https://lcsc.com/product-detail/CPLD-FPGA_XILINX_XC7A35T-2FTG256C_XC7A35T-2FTG256C_C181716.html

I think this one is 6gb/sec...
And there is stock.

Unfortunately this package does not bond out any transceivers.

Odd, I thought that the big red 'XC7A35T' meant it has the transceivers bonded out.
What would be the purpose of paying extra for that 'T' when the cheaper ones without are available for 7$.

However, you appear to be right...

I guess you are stuck with this 35$ monster:
https://lcsc.com/product-detail/CPLD-FPGA_XILINX-XC6SLX45T-3FGG484C_C569030.html

[asmi]

Odd, I thought that the big red 'XC7A35T' meant it has the transceivers bonded out.
What would be the purpose of paying extra for that 'T' when the cheaper ones without are available for 7$.

Nope, actual silicon always contains transceivers, but in some packages they are not bonded out and lasered out on the die to make sure they don't waste power.
You just need to know which packages have them bonded out, and which ones don't. At least Xilinx provides excellent guide UG475, which includes graphic diagrams so you can easily see what is available in specific package. No other vendor to my knowledge does that, which is super weird. This of course is listed in the datasheet, but I prefer those diagrams because they contain a lot of information if you know how to read it.

I guess you are stuck with this 35$ monster:
https://lcsc.com/product-detail/CPLD-FPGA_XILINX-XC6SLX45T-3FGG484C_C569030.html

There is smaller 0.8 mm pitch package CSG325, which also bonds out a full transceiver quad (4 transceivers).

[miken]

Lattice has a new Crosslink-NX family that would seem to be a good fit for this use case. But the usual new product caveats apply as regards sourcing and support...

[Yansi]

Someone mentioned silicon dies are shared between some of the devices, so similar question comes into mind: What is limiting the smaller density Cyclone IV GX FPGAs at the specified 2.5Gbps transceiver rate?

Thinking about all of them being in the same family, probably exact same silicon technology and very similar if not exact same transceiver design, why the smaller ones are specified only for 2.5Gbps?

2.5 and 3 Gbps is not as much of difference, so what makes it?

Not that I plan to try abusing them to 3Gbps, but I mean, seriously, why the smaller package is limited to work at 2.5G, while the huge BGAs are cpable of doing 3G?   Isn't this just marketing by any chance?

[asmi]

Someone mentioned silicon dies are shared between some of the devices, so similar question comes into mind: What is limiting the smaller density Cyclone IV GX FPGAs at the specified 2.5Gbps transceiver rate?

Not that I plan to try abusing them to 3Gbps, but I mean, seriously, why the smaller package is limited to work at 2.5G, while the huge BGAs are cpable of doing 3G?   Isn't this just marketing by any chance?

It might be that their characterization results showed that some packages can not be guaranteed to work in entire PVT range. Remember that when FPGA vendor says "it can do X" what they really mean is "it can ALWAYS do X, no matter if it's -40°C cold or +105°C hot, if it's powered by 0.95 V or 1.05 V, in any combination of those parameters as long as each of them is within supported range".
For example, that is the reason Spartan-7 in BGA196 package can only drive DDR3 at 333 MHz and not 400 MHz like all other packages can. That gets even worse as your bitrate goes into Gbps range. For example, the very same Kintex-7 silicon can go as low as 6.6 Gbps or as high as 12.5 Gbps depending on a package it's in! And before you begin inventing conspiracies, the cheapest package is not the slowest one, in fact it's closer to the fastest (see attachment for the speed grade -3).

[BrianHG]

Someone mentioned silicon dies are shared between some of the devices, so similar question comes into mind: What is limiting the smaller density Cyclone IV GX FPGAs at the specified 2.5Gbps transceiver rate?

Thinking about all of them being in the same family, probably exact same silicon technology and very similar if not exact same transceiver design, why the smaller ones are specified only for 2.5Gbps?

2.5 and 3 Gbps is not as much of difference, so what makes it?

Not that I plan to try abusing them to 3Gbps, but I mean, seriously, why the smaller package is limited to work at 2.5G, while the huge BGAs are cpable of doing 3G?   Isn't this just marketing by any chance?

Just the quality of the silicon and routing to the BGA's package pad.
In the -GX, the -8 and some -7 are 2.5-2.7gbps while the -6 are 3gbps.  Raise the v-core by 50-100mv and you will get full -6 performance on a -8 part with a little more power consumption.  Just tell Quartus your pcb has a -6.  If you cannot get the 3gbps because of your package selection, even with a -6, do the same with the core supply and when configuring the PLL, underrate the CLK input setting by 17% compared to your true crystal value only if you need to to actually achieve a compile.  Usually Quartus will still compile for the 3gsps, but just give you a timing violation warning.

It also helps if you have a good cable driver amp at the output of the LVDS IO  transmitter pins, especially if that driver has some signal gain in the 3GHz frequency range.
The LVDS receivers seem to tolerate much better when being overclocked, however this is usually because you are feeding the input pins a really fast and clean signal which gets terminated on the die.