Electronics > FPGA

Port <i_Clk50MHz> has illegal connections.

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ali_asadzadeh:
Hi,
I have a 50MHz input clock and I wanted to use a DCM to generate a 96MHz clock, also I want to use the 50MHz clock to drive some parts of my design, the device is Spartan 6, But ISE would complain about

--- Quote ---Port <i_Clk50MHz> has illegal connections. This port is connected to an input buffer and other components.
--- End quote ---

Here is my simple code


--- Code: ---module top (
    //Clock
    input i_Clk50MHz,
//ADCs
output [8:0] o_AdcSck,
input [8:0] i_AdcSdo,
input [8:0] i_AdcBusy,
//Leds
output [11:0] o_led
);

//Regs and wires decleration****************************************************************
//96MHz clock generation
wire w_CLK96MHz;
wire w_PllLocked;
wire w_Reset;
reg r_600KHzClk;
reg [7:0] r_cnt600KHz = 8'h0;


wire wAdcDv;
wire [15:0] wAdcData;

reg [31:0] r_cnt = 32'h0;

//End Regs and wires decleration****************************************************************


//assign w_CLK96MHz = i_Clk50MHz;
Clock96MHz my96MHzclk(
.CLK50_IN(i_Clk50MHz),
.CLK96_OUT(w_CLK96MHz),
.LOCKED(w_PllLocked)
);
//Chipsope Connections End****************************************************************
assign w_Reset = ~w_PllLocked;

LTC2378 ADC8(
    .i_Clk(i_Clk50MHz),
    .i_Rst(w_Reset),
    .o_Data(wAdcData),
.o_DV(wAdcDv), //output data valid

//physical pins
.i_DRDY(i_AdcBusy[8]),
//SPI Master module physical pins
    .i_MISO_pin(i_AdcSdo[8]),
    .o_SCLK_pin(o_AdcSck[8])
);

wire [12:0] addra;
wire [15:0] douta;

SinTable sinTable (
  .clka(w_CLK96MHz), // input clka
  .addra(addra), // input [12 : 0] addra
  .douta(douta) // output [15 : 0] douta
);

wire [15:0] doutb;
CosTable cosTable (
  .clka(w_CLK96MHz), // input clka
  .addra(addra), // input [12 : 0] addra
  .douta(doutb) // output [15 : 0] douta
);


assign o_AdcSck[7:0] = 0;

always @(posedge w_CLK96MHz) begin
r_cnt <= r_cnt + 1'b1;
end
assign o_led[9:0] = ~r_cnt[31:22];
assign o_led[11:10] = Vio[7:6];

//600KHz ADC clock convertion
always @(posedge w_CLK96MHz) begin
r_cnt600KHz <= r_cnt600KHz + 1'b1;
if(r_cnt600KHz == 8'd160) begin
r_cnt600KHz <= 0;
end

if(r_cnt600KHz <= 8'd80) begin
r_600KHzClk <= 1'b1;
end else begin
r_600KHzClk <= 1'b0;
end
end

assign o_FPGA_ADC_CLKP = r_600KHzClk;


endmodule

--- End code ---

What I have done wrong?

SMB784:
Is the connection between i_clk50mhz and the input of ADC8 intentional?  Did you mean to connect clk96mhz instead?

ali_asadzadeh:

--- Quote ---Is the connection between i_clk50mhz and the input of ADC8 intentional?
--- End quote ---
Yes, I want this part of the design works with 50MHz, and the other parts work with 96MHz.

miken:
Any reason why you can't have the DCM make a 50 MHz output, and run all your 50 MHz stuff on that?

ali_asadzadeh:

--- Quote ---Any reason why you can't have the DCM make a 50 MHz output, and run all your 50 MHz stuff on that?
--- End quote ---
My input clock is a low jitter clock.

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