Port <i_Clk50MHz> has illegal connections.

[ali_asadzadeh]

Hi,
I have a 50MHz input clock and I wanted to use a DCM to generate a 96MHz clock, also I want to use the 50MHz clock to drive some parts of my design, the device is Spartan 6, But ISE would complain about

Port <i_Clk50MHz> has illegal connections. This port is connected to an input buffer and other components.

Here is my simple code

Code: [Select]

module top (
    //Clock
    input i_Clk50MHz,
//ADCs
output [8:0] o_AdcSck,
input [8:0] i_AdcSdo,
input [8:0] i_AdcBusy,
//Leds
output [11:0] o_led
);

//Regs and wires decleration****************************************************************
//96MHz clock generation
wire w_CLK96MHz;
wire w_PllLocked;
wire w_Reset;
reg r_600KHzClk;
reg [7:0] r_cnt600KHz = 8'h0;


wire wAdcDv;
wire [15:0] wAdcData;

reg [31:0] r_cnt = 32'h0;

//End Regs and wires decleration****************************************************************


//assign w_CLK96MHz = i_Clk50MHz;
Clock96MHz my96MHzclk(
.CLK50_IN(i_Clk50MHz),
.CLK96_OUT(w_CLK96MHz),
.LOCKED(w_PllLocked)
);
//Chipsope Connections End****************************************************************
assign w_Reset = ~w_PllLocked;

LTC2378 ADC8(
    .i_Clk(i_Clk50MHz),
    .i_Rst(w_Reset),
    .o_Data(wAdcData),
.o_DV(wAdcDv), //output data valid

//physical pins
.i_DRDY(i_AdcBusy[8]),
//SPI Master module physical pins
    .i_MISO_pin(i_AdcSdo[8]),
    .o_SCLK_pin(o_AdcSck[8])
);

wire [12:0] addra;
wire [15:0] douta;

SinTable sinTable (
  .clka(w_CLK96MHz), // input clka
  .addra(addra), // input [12 : 0] addra
  .douta(douta) // output [15 : 0] douta
);

wire [15:0] doutb;
CosTable cosTable (
  .clka(w_CLK96MHz), // input clka
  .addra(addra), // input [12 : 0] addra
  .douta(doutb) // output [15 : 0] douta
);


assign o_AdcSck[7:0] = 0;

always @(posedge w_CLK96MHz) begin
r_cnt <= r_cnt + 1'b1;
end
assign o_led[9:0] = ~r_cnt[31:22];
assign o_led[11:10] = Vio[7:6];

//600KHz ADC clock convertion
always @(posedge w_CLK96MHz) begin
r_cnt600KHz <= r_cnt600KHz + 1'b1;
if(r_cnt600KHz == 8'd160) begin
r_cnt600KHz <= 0;
end

if(r_cnt600KHz <= 8'd80) begin
r_600KHzClk <= 1'b1;
end else begin
r_600KHzClk <= 1'b0;
end
end

assign o_FPGA_ADC_CLKP = r_600KHzClk;


endmodule

What I have done wrong?

[SMB784]

Is the connection between i_clk50mhz and the input of ADC8 intentional?  Did you mean to connect clk96mhz instead?

[ali_asadzadeh]

Is the connection between i_clk50mhz and the input of ADC8 intentional?

Yes, I want this part of the design works with 50MHz, and the other parts work with 96MHz.

[miken]

Any reason why you can't have the DCM make a 50 MHz output, and run all your 50 MHz stuff on that?

[ali_asadzadeh]

Any reason why you can't have the DCM make a 50 MHz output, and run all your 50 MHz stuff on that?

My input clock is a low jitter clock.

[SiliconWizard]

Any reason why you can't have the DCM make a 50 MHz output, and run all your 50 MHz stuff on that?

My input clock is a low jitter clock.

You're going to have to handle synchronization between the two clock domains if you insist on keeping the original 50 MHz oscillator, and generate an extra clock from it with a DCM.

The most usual way of doing this is to instantiate a DCM with your 50 MHz clock as an input, and two clock outputs, one of them being 50 MHz. The DCM block will ensure a given phase relationship between the two outputs, and additionally, you'll know both clocks are going to be distributed through dedicated clock distribution trees. The downside is, as you guessed, the resulting jitter may not be as good as your original oscillator.

Although we may be lacking some info for your particular project, I'm assuming the Xilinx tools are unable to both route your 50 MHz clock input to a DCM input and to a general-purpose clock distribution tree at the same time.

[miken]

Well, whenever you take a clock into an FPGA and back out again, it's likely going to be degraded somewhat even if it doesn't go through a DCM. Better make sure it still meets your requirements.

Xilinx usually allows less-ideal route paths if you ask for them, but I'm not familiar with Spartan-6. Read the Clocking Resources manual for all the juicy details.

[ali_asadzadeh]

Thanks for the feedbacks.

[SiliconWizard]

Note that if this is an internal routing problem, you may want to try the following: externally feed your 50 MHz clock to two FPGA inputs instead of just one, both being GCLK pads. Then you'll use one as your 50 MHz clock, and the other as the input for a DCM. You can try that virtually of course - just modify your RTL and your UCF file (to have 2 clock inputs instead of 1), and see if it solves your problem. If so, you'll need of course to physically route your clock input to two pads instead of one accordingly.

Note again that if you use this clocking scheme, you'll need to handle sync between the two clock domains.