Power measurements of a PLL

[steamedhams]

I am currently doing characterization of a PLL on an FPGA.

I am thinking about some meaningful measurements.

I am not sure if I just sweep the frequency and measure the current consumption or is there anything else worth measuring when it comes to power.

Perhaps the ramp up current usage before the PLL is locked.

 

[FlyingDutch]

Hi,

you can also measure: "jitter" and "phase shift">

Regards

[steamedhams]

It is only focused around power consumption.

[SiliconWizard]

Ramp-up current? I guess you mean the current draw from the moment you enable it to the moment it's locked? Not sure you'll see anything really interesting compared to its steady-state current, but why not. For this you'll need to write proper HDL code - for instance toggling an IO when you enable the PLL and toggling it back when it's locked, so you can synchronize you measurement. Then you'll need a proper dynamic measurement of current - I'm assuming you already have this setup.

As to "sweep the frequency", it's a bit trickier here I guess. The power consumption of a PLL will depend on the input frequency, VCO frequency and the various dividers - not just the output frequency.
That may be a lot of configurations to test.