Author Topic: Problem in Generate  (Read 616 times)

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Online ali_asadzadeh

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Problem in Generate
« on: September 18, 2021, 09:14:55 am »
Hi,
I have 9 channels of FIR filter, which would produce 31 bit output data, I want to trim them and use generate to connect all of them to some output module.

Here is my code

Code: [Select]
wire signed [30:0] wIFir,wQFir [0:8];
wire signed [15:0] wIFirTrim,wQFirTrim [0:8];

genvar i;
generate
for (i = 0; i< 9; i = i +1) begin
assign wIFirTrim[i] = wIFir[i][25:10];//extract the 16 bit valuable data
assign wQFirTrim[i] = wQFir[i][25:10];
end
endgenerate

But ISE would complain that wIFir is not a memory!

what I have done wrong?
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Offline cruff

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Re: Problem in Generate
« Reply #1 on: September 18, 2021, 12:37:11 pm »
I scanned the SystemVerilog standard briefly, and it seems to me that you might need to use these declarations to declare wIFir and wIFirTrim as arrays:

Code: [Select]
wire signed [30:0] wIFir[0:8], wQFir[0:8];
wire signed [15:0] wIFirTrim[0:8], wQFirTrim[0:8];
 
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Online ali_asadzadeh

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Re: Problem in Generate
« Reply #2 on: September 18, 2021, 12:45:15 pm »
Thanks cruff :-+
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Offline radiolistener

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Re: Problem in Generate
« Reply #3 on: October 14, 2021, 02:51:48 am »
Note: if you simply cut-off unused bits for truncation, you will get unwanted DC spur on the output. As result your truncated output will be distorted with unwanted bias offset.

For example it happens when you get just 10 or 16 bits from 31 bit FIR output. In order to avoid it, you're needs to use rounding.

Here is article for more details.
« Last Edit: October 14, 2021, 03:00:39 am by radiolistener »
 
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Online ali_asadzadeh

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Re: Problem in Generate
« Reply #4 on: October 14, 2021, 01:55:18 pm »
thanks
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I'm a Digital Expert from 8-bits to 64-bits
 


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