Electronics > FPGA

Problem in Generate

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ali_asadzadeh:
Hi,
I have 9 channels of FIR filter, which would produce 31 bit output data, I want to trim them and use generate to connect all of them to some output module.

Here is my code


--- Code: ---wire signed [30:0] wIFir,wQFir [0:8];
wire signed [15:0] wIFirTrim,wQFirTrim [0:8];

genvar i;
generate
for (i = 0; i< 9; i = i +1) begin
assign wIFirTrim[i] = wIFir[i][25:10];//extract the 16 bit valuable data
assign wQFirTrim[i] = wQFir[i][25:10];
end
endgenerate
--- End code ---

But ISE would complain that wIFir is not a memory!

what I have done wrong?

cruff:
I scanned the SystemVerilog standard briefly, and it seems to me that you might need to use these declarations to declare wIFir and wIFirTrim as arrays:


--- Code: ---wire signed [30:0] wIFir[0:8], wQFir[0:8];
wire signed [15:0] wIFirTrim[0:8], wQFirTrim[0:8];
--- End code ---

ali_asadzadeh:
Thanks cruff :-+

radiolistener:
Note: if you simply cut-off unused bits for truncation, you will get unwanted DC spur on the output. As result your truncated output will be distorted with unwanted bias offset.

For example it happens when you get just 10 or 16 bits from 31 bit FIR output. In order to avoid it, you're needs to use rounding.

Here is article for more details.

ali_asadzadeh:
thanks

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