| Electronics > FPGA |
| problem with AXI bus |
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| e0ne199:
Hello everyone, i have a problem with sending data over AXI bus. The data I want to send is an array of int (392 row and 30 column), but when I try to send it with AXI stream, the AXI stream throws an error...do you know what to do in this situation? any response is really appreciated, thx before. |
| Someone:
--- Quote from: e0ne199 on December 31, 2024, 05:52:15 am ---but when I try to send it with AXI stream, the AXI stream throws an error... --- End quote --- Which error? You will need to share many more details to get help/advice. An AXI Stream endpoint/sink provides no status/error/reporting, it is either accepting data or it is not. |
| Siwastaja:
If --- Code: ---if (status != XST_SUCCESS) --- End code --- is failing, then the obvious thing to do is to print the value of status and compare it to the documentation of XAxiDma_SimpleTransfer(), which can be found with 5 seconds of Googling: https://xilinx.github.io/embeddedsw.github.io/axidma/doc/html/api/group___a_x_i_d_m_a.html#ga32ca6099d7926297a4c17cdb4a19511b --- Code: ---Returns XST_SUCCESS for success of submission XST_FAILURE for submission failure, maybe caused by: Another simple transfer is still going XST_INVALID_PARAM if:Length out of valid range [1:8M] Or, address not aligned when DRE is not built in --- End code --- |
| e0ne199:
--- Quote from: Siwastaja on December 31, 2024, 12:27:32 pm ---If --- Code: ---if (status != XST_SUCCESS) --- End code --- is failing, then the obvious thing to do is to print the value of status and compare it to the documentation of XAxiDma_SimpleTransfer(), which can be found with 5 seconds of Googling: https://xilinx.github.io/embeddedsw.github.io/axidma/doc/html/api/group___a_x_i_d_m_a.html#ga32ca6099d7926297a4c17cdb4a19511b --- Code: ---Returns XST_SUCCESS for success of submission XST_FAILURE for submission failure, maybe caused by: Another simple transfer is still going XST_INVALID_PARAM if:Length out of valid range [1:8M] Or, address not aligned when DRE is not built in --- End code --- --- End quote --- yes I am aware of the error..my problem is i don't know why i am unable to send arrays larger than 30x10 to the PL side...i am still very new to verilog especially AXI communications, and i am not sure if the AXI faces bottleneck or something like that when i try to send large data using AXI stream..do you have any suggestions about that, for example where to look for this kind of problem? or do i have to do some configuration (or add some IP block) on the PL side? |
| Someone:
Where is the AXI stream in this? The code example supplied is using some high level software to interact with a DMA engine. --- Quote from: e0ne199 on December 31, 2024, 01:45:27 pm ---yes I am aware of the error..my problem is i don't know why i am unable to send arrays larger than 30x10 to the PL side...i am still very new to verilog especially AXI communications, and i am not sure if the AXI faces bottleneck or something like that when i try to send large data using AXI stream..do you have any suggestions about that, for example where to look for this kind of problem? or do i have to do some configuration (or add some IP block) on the PL side? --- End quote --- So you want to send data to the PL, but dont have anything on the PL side? This sounds like you're just throwing stuff at a wall with no plan of how it should function. |
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