Problems with a 16V8 Frequency Divider (SOLVED)

[ChewChew]

Problem

A simple 1MHz frequency divider implemented in a 16V8 doesn’t perform as expected. 

The output does not have a 50% duty cycle and sporadically flat-lines for a few cycles.  The results are quite inconsistent and once I managed to get a nice clean 50% duty cycle, but I cannot work out why so consequently I haven't been able to repeat that since. 



More Details

I’m trying to condense a few TTL gates into a 16V8.  The circuit works 100% using discrete gates, but only 75% using a 16V8.  The 25% non-functioning bit is the frequency divider so I stripped out all the other code to concentrate on resolving that piece, but no luck so far.

I have:

• tested on both GAL16V8D-25 and ATF16V8B-10 devices
  Tried different input and output pin combinations
  Played with decoupling capacitors
  Grounded unused inputs and outputs

All with the same results. 

This is my first adventure into PLDs since playing with Xilinx 20+ years back at university so I’m guessing that I’m missing some subtle secret sauce.

I’m using WinCUPL and everything tests fine in WinSIM. 

Code: [Select]

Device   g16v8a ;

/*           ------- */
/* CK |1 20| Vcc */
/* X |2 19| CKlp */
/* HD |3 18| oscff */
/* X |4 17| RDY */
/* MTR |5 16| I/O */
/* X |6 15| ff1 */
/* DS |7 14| I/O */
/* X |8 13| oscot */
/* oscin |9 12| c */
/* GND |10 11| !OE */
/*        ------- */


/* *************** INPUT PINS *********************/
PIN   1  = CK     ; /* OSC input    */


/* *************** OUTPUT PINS *********************/

PIN   18  = oscff ; /* 1/2 OSC freq FF output  */


/* ***************** LOGIC ********************** */

oscff.d = !oscff ;



[Andy Watson]

How fast is your clock? Does it have fast rise and fall times? Free from overshoot?

 

[TomS_]

It looks like you have some glitches in your trace which might suggest a bad probing setup. How are you probing the output and have you got a good solid ground between the circuit and the logic analyser?

[BrianHG]

Can we see an analog scope shot of the clock input?

It may be a marginal signal which has a little voltage bias at startup, then settles into a voltage swing which your logic analyzer still sees as clean, but does not cleanly cross the threshold required for the 16V8's logic clock input.  IE: CMOS VS TLL threshold levels.  Or a weak clock.  Also, more stringent power decoupling caps for PAL/GAL devices are required much more than normal TTL logic devices.

[ChewChew]

Thanks to those who posted replies.

It looks like the next step is to take a proper look at the clock with an oscilloscope.  I will borrow one from work and report back my findings.
 

[ChewChew]

Right, I’ve done some probing -

• The first picture is the 1 Mhz input. 
• The second is the GAL output at 500 KHz when it is not connected to the input of the next device. 
• The third is the GAL output at 500 KHz when it is connected to the input of the next device.   

I did some experimenting -

• Using a NAND (74LS00) to buffer the output of the GAL worked - see fourth picture.
• Using a D (74LS74) as a frequency divider worked - see fifth picture.
• I reconfigured the GAL just to pass through the 1 MHz clock and this worked flawlessly. 
• Pullup or pulldown resistor makes no difference. 

I can’t work out why the GAL supplying a clock signal at 1 MHz works, but at 500 KHz it does not work.

Any ideas, please?

[ChewChew]

OK, i think I've found a work around by configuring the ouput to go high Z on low and using a 4.7K pulldown resistor.

Still confused why it works using TTL gates but not with the GAL, that is with the above fudge.

[BrianHG]

Your CLK in seems to have a dent in it at the trigger point, so your gal is counting twice quickly at the rise of the clk in.  It seems your scope or probe doesn't have the full bandwidth to really see it as anything more than just a fuzzy dent at the ~2.0v - 2.3v region.

Here is a test, try a pull-up resistor on the CLK in pin to VCC.  Something like 220ohm, or 150ohm.
Another fix may be adding a 0.1uf cap from VCC to GND across the GAL's supply pins.  If there is a drop in the GAL's supply during the output toggle, it may see a double clock event.

[tggzzz]

Are you by any chance testing the circuit on a solderless breadboard? If so you may find yourself spending more time debugging the breadboard than your design.

In any case, show a photo of your experimental setup.

[BrianHG]

Questions: Do you have a bunch of unused input pins left floating?
This is less of a problem on a real PCB, but with a bread board, fast toggle signals will bridge from pin to pin as tiny pulses.

[ChewChew]

Hey, Many thanks to BrianHG and tggzzz for your comments and suggestions.

Taking each in order -

I will try a pullup on the CK and report back next time I play with this.

I’ve tried capacitors across both the supply and the supply pins to the IC with no change.

Yes, I’m prototyping on a breadboard.  See picture.

I’ve tried grounding unused inputs with no change.

[tggzzz]

Yes, I’m prototyping on a breadboard.  See picture.

When I'm presented with such things, I refuse to look at them Why, and for better techniques see
https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/

For an illustration of why wire length matters, see
https://entertaininghacks.wordpress.com/2015/04/23/scope-probe-accessory-improves-signal-fidelity/

[ChewChew]

Yes, I’m prototyping on a breadboard.  See picture.

When I'm presented with such things, I refuse to look at them Why, and for better techniques see
https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/

LOL and it worked so well and repeatedly with discrete logic gates……

For an illustration of why wire length matters, see
https://entertaininghacks.wordpress.com/2015/04/23/scope-probe-accessory-improves-signal-fidelity/

Again, this worked with discrete logic and its all asynchronous.  The ‘clock’ is just a reference frequency for the motor driver IC.  This is halved under certain conditions fed into the GAL from the other wires to slow the motor down from 300 rpm to 150 rpm. 

I guess the GAL is not as tolerant as 74LS gates. Or is it more responsive ..... 

Many thanks for the links.  Very interesting.

[tggzzz]

Yes, I’m prototyping on a breadboard.  See picture.

When I'm presented with such things, I refuse to look at them Why, and for better techniques see
https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/

LOL and it worked so well and repeatedly with discrete logic gates……

For an illustration of why wire length matters, see
https://entertaininghacks.wordpress.com/2015/04/23/scope-probe-accessory-improves-signal-fidelity/

Again, this worked with discrete logic and its all asynchronous.  The ‘clock’ is just a reference frequency for the motor driver IC.  This is halved under certain conditions fed into the GAL from the other wires to slow the motor down from 300 rpm to 150 rpm. 

Many thanks for the links.  Very interesting.

You're welcome.

V_induced=L*^di/_dt, and that's bad if it "appears" in the ground or Vcc connections since it changes the logic levels "seen" by the inputs and "sent" from the outputs.

Modern logic is faster (=> reduced dt), can drive higher currents particularly when output is high (=> higher di), can have more outputs switching (==>  higher di), and those flying leads are lots of inductance. Everything works against solderless breadboards. Estimate L, di, dt and do the arithmetic; you should be unpleasantly surprised.
I guess the GAL is not as tolerant as 74LS gates. Or is it more responsive ..... 

[ChewChew]

So I ditched the breadboard and went rats nest and everything worked as expected.

Lesson learnt 

Many thanks to those who posted suggestions and special thanks to tggzzz

[tggzzz]

So I ditched the breadboard and went rats nest and everything worked as expected.

Lesson learnt 

Many thanks to those who posted suggestions and special thanks to tggzzz

Always a pleasure to help, and to enable people to have more fun in the future