Author Topic: Programming (non-JTAG) MAX7000 devices  (Read 48775 times)

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Offline pityokas

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #125 on: August 18, 2022, 09:41:57 am »
http://matthieu.benoit.free.fr/all03/adp-7064S-PL84/
http://matthieu.benoit.free.fr/120.htm
My adapter is compatible with all MAX 7000 PLCC84 packages for ALL-03?
No really help because no names on pins just connection so I can't identify after waveform.
But found interesting, only the SDOABCD pins are connected to pullup, maybe not needed in programming.

https://forum.system-cfg.com/viewtopic.php?f=18&t=13192
They talking about enable MAX7000S JTAG, I don't have problem to program any S type PLD.


All MAX7000S compatible because using JTAG pins, but the MAX7000 are not!
 

Offline Beta_vulgaris

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #126 on: August 18, 2022, 09:51:44 am »
1568626-0
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Offline pityokas

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #127 on: August 18, 2022, 11:29:40 am »
(Attachment Link)
Ok let explain what I know and what no from this schematic compared with my adapter and my waveform:
Clocks: Pin 31,79,83 buffers, probably clock,ok, match my waveform.
SCO-s: Pin 4,23,62,81 trough 244 output, match my waveform
SDI-s: Pin 20,39,46,65 trough 244 input-> match
SDO-s: Pin 10,29,56,75 pullup, my waveform at initialization are all 4 set to high -> match
Missing: Pin 36,37,41,44,48,49,71 and some others,there are directly connected to zif, how to determine the position?
Maybe if migry generate a valid waveform for my epm ID, I can compare else this schematic not help more.

BTW my EPM7064-84 ID: 41 4C 54 45 52 41 39 37 A3 01 00 00 00 (ALTERA97) A301 probably revision and programming info
« Last Edit: August 18, 2022, 11:37:00 am by pityokas »
 

Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #128 on: August 18, 2022, 12:36:30 pm »
I have been looking at this schematic and using it to try to emulate the epm7064 in my DOSBOX-X code base.

I think that pin 1 of the ZIF is incorrect. PLEASE SEE BELOW, this was written before thinking more fully (sorry!).

It is labelled pin35 (not apparently used for programming), but I think that it should be pin25, which is AD0. SEE BELOW (the adapter diagram could be incorrect ?).

ZIF pins 1 to 7 were AD0 to AD6 for the EPM7032, but once I had mapped the pins, I saw that AD0 of the EPM7064 was not connected.
Pins 1 to 8 map to ALL03 register "E0" and was used for the ADDR bus on the EPM7064 and I would assume that this was not changed for the EPM7064.

ADDED LATER: Apologies. It could be the picture of the pin out of the EPM7064 which is incorrectly labelled. In other words perhaps pin 35 is AD0, rather than pin25 ?

I now also note that pin 21 of the ZIF connects to SS_BI (waveform is the same as SS on the 7032).
The diagram of the adapter shows SS_BI on pin 73, but the schematic shows this pin going to pin 77 of the 84 pin PLCC device.

I note that BE is on pin 6 according to the adapter diagram, but I see no control of this from the schematic (just a pull-up).
In the schematic I see pin 19 of the ZIF socket connects to pin 69, but in the adapter diagram this does not show a test purpose.
In the schematic I see pin 36 of the ZIF socket connects to pin 16, but in the adapter diagram this does not show a test purpose.

In the adapter diagram the boxes coloured GREEN seem to indicate something special, but pin 16 shows no test purpose, ditto for 35 and 69.
It just makes me wonder if 16 is BE, 35 is AD0, and 69 is  SS_BI or TM ?

I wonder if it possible to determine which diagram is incorrect ?
« Last Edit: August 18, 2022, 01:15:44 pm by migry »
 

Offline pityokas

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #129 on: August 18, 2022, 01:02:53 pm »
Pins 25 and 35 not seems to be used.
Use this for input simulation.Do not skip the ID check, let the program decide what to do with information!
The vpp is still not connected. I did not make an input circuit for high voltage :)
« Last Edit: August 18, 2022, 01:06:43 pm by pityokas »
 

Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #130 on: August 18, 2022, 01:20:39 pm »
Pins 25 and 35 not seems to be used.
Use this for input simulation.Do not skip the ID check, let the program decide what to do with information!
The vpp is still not connected. I did not make an input circuit for high voltage :)

I'm pretty sure one of these two pins is AD0.
You would need to do a blank checks, which increments the address by one, to confirm.

BTW I am still unclear as to your setup. Can you take a picture for clarification?

Am I correct in understanding that you have a BeeProg programmer which you are using to capture the waveforms from?

Have you made a home-brew adapter fro the 40 pin ZIF to the 84 pin PLCC ?

Is this what you are trying to debug ?
 

Offline Beta_vulgaris

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #131 on: August 18, 2022, 01:32:16 pm »
I wonder if it possible to determine which diagram is incorrect ?
I recalled that the inner ring was EPM7032, NOT 7064? I forgot where I saw it.
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Offline pityokas

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #132 on: August 18, 2022, 01:35:51 pm »
Quote
Am I correct in understanding that you have a BeeProg programmer which you are using to capture the waveforms from?
Yes

Quote
Have you made a home-brew adapter fro the 40 pin ZIF to the 84 pin PLCC ?
PLCC84 to ZIF48

And yes I'm try to debug my adapter.
 
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Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #133 on: August 18, 2022, 02:26:28 pm »
(Attachment Link)

Is this your work at reverse engineering the adapter socket?

Or do you know who created the schematic?

At this point in time I am leaning towards believing this schematic, and thinking that the pin out (rectangle) diagram has some bugs.

Nevertheless I wonder where the person who created the diagram got the test pin names from?

Note: the 7032 only has SCOA/SCOB, where as the 7064 has SCOA/B/C and D.

This ties up with the fact that the ALL03 has an executable for the 7032 (only) and a different executable which supports the 7064/7096 and 7128.
The former "knows" about 2 serial read channels and the latter 4 (I will check my disassembly of the latter code to confirm).
 

Offline Beta_vulgaris

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Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #135 on: August 18, 2022, 07:26:33 pm »
Pins 25 and 35 not seems to be used.
Use this for input simulation.Do not skip the ID check, let the program decide what to do with information!
The vpp is still not connected. I did not make an input circuit for high voltage :)

I have had a look at your traces, and I have found it difficult to understand them. The software used by the BeeProg might well stimulate the device in a different order.
Interestingly I see 3 pins which are unlabelled on the adapter diagram, but could be SDOUTB, C and D. Not that these pins show anything of interest anyway!

I have created a version of DOSBOX-X with an emulation of the EPM7064 device, and traces based around the pin mapping from the schematic (and some from the diagram). It isn't working in that the EPM7064 is not recognised, so the ALL03 software does not proceed further. The first thing that it always does is look for the device ID. For some reason it is not being seen, even though I am generating the same serial bit stream on SCOA as was done on the EPM7032.

Here are the traces. One difference between these and yours is that I see activity on "SS_BI" and yours is always zero.
NOTE: I may have some pins labelled incorrectly due to not knowing if the adapter diagram labels are correct.
 

Offline Beta_vulgaris

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #136 on: August 19, 2022, 12:31:59 am »
NOTE: I may have some pins labelled incorrectly due to not knowing if the adapter diagram labels are correct.
Some of the inner labels are for EPM7032, I remembered, if I were correct.
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Offline pityokas

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #137 on: August 19, 2022, 04:39:01 am »
Here are the traces. One difference between these and yours is that I see activity on "SS_BI" and yours is always zero.
Interesting why SCOA=SCOB=SCOC=SCOD?
SCO is output, from where you get the data?
Also I don't understand why bee using 17 clock pulses for SK and ALL only 16?
Can you put a break-point on ID check just feed my ID ad let run?
SS_BI(pin 73) on ALL adapter connected to pulldown. I think you mislabeled, that pin is BV(pin71) and will be similar to my waveform.

Another interesting difference: ALL use SCK pulses after each data read, bee not, but bee using extra SK pulses and ALL not
Bee send 80 SCK pulses ALL send 90? counted right? can you expand and count?

Hint: if you can export your data as binary then you can import into pulseview and there is more tools like counter spi demodulator.
« Last Edit: August 19, 2022, 06:44:54 am by pityokas »
 

Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #138 on: August 19, 2022, 12:50:02 pm »
Interesting why SCOA=SCOB=SCOC=SCOD?
SCO is output, from where you get the data?

All SCO outputs are the same because this is a trace from an emulated EPM7064.

Going back to the EPM7032 and the ALL03 software...
I compiled DOSBOX-X from sources. I can then run dosbox-x and load the ALL03 binary (AMAX70.EXE for the EPM7032). I then added my own module. This module emulates   1) the ISA card and the PAL protection(?) circuitry 2) the registers of the ALL03 programmer (e.g. there are 5 8 bit registers for driving the 40 pins of the ZIF socket, but there are others too) 3) the EPM7032.
As I mentioned the ALL03 software will not generate the proper waveforms unless the check for the ISA card is OK and also the check for the device in the socket (i.e. device ID read) is OK too. So once I had genuine traces from real silicon (the 7032V) for SCOA and SCOB, I added emulation of this to the code. After this was debugged the ALL03 programmer code is happy that it is seeing a genuine device and generates the full set of waveforms for all programming actions. It does however barf during programming because I do not emulate the EEPROM memory.

I trace the waveforms by writing "special" data to the LOG file. I then extract this data and create the stimulus in Verilog format. Weird yes!  ;D I have a Verilog testbench which I compile and simulate to generate the waveforms. There is no option to save waveforms AFAIK., but you could write Verilog code to write a binary file. How to make this compatible with Pulseview - I have no idea.

I copied the DOSBOX-X EPM7032 area and created a EPM7064 area and modified the emulation of the MAX device to reflect the change of pins, and I added SDINC, SDIND, SCOC and SCOD. I emulate the SCO pins, so what you see is my guess at their behaviour and is NOT from a real device. For some reason the device ID was not working for the EPM7064 (it DOES work for the '32). The device ID for the EPM7032 comes out of the SCOA pin. I simply copied the SCOA waveform into the B,C and D eumulation in case the software was looking for the device ID on a different pin.

I am very happy with these waveform traces for the EPM7032. This is way I am CERTAIN than your SS waveform is incorrect.

I then re-generate the waveforms on my desktop setup. There are photos earlier in this thread if you are interested. I use an Arduino to generate the stimulus.

Also I don't understand why bee using 17 clock pulses for SK and ALL only 16?
Can you put a break-point on ID check just feed my ID ad let run?

The sequence comes from the ALL03 software, however the TIMING is NOT accurate. I only log I/O writes and reads. My waveform is sort of like a condensed version of the stimulus. I t would look more like your capture on real ALL03 hardware (which I do not have - and is unavailable in the UK at a sensible price if at all).

Thanks to the IDA Pro work, I am confident that the waveforms are 100% correct, and they do have a sensible pattern. Perhaps without the software delay adding gaps it is less easy to spot each sub-sequence.

I was unable to determine the serial data for the ID from your waveforms, since they look so different to the ones from the ALL03 which I am used to.

I will use DOXBOX-X instruction trace to figure out why the device ID datastream is not working, but from initial look at the IDA Pro disassembly the code is more or less the same.



I hope this clarifies.

BTW I can go into more detail, but most readers are probably not interested. If you have specific questions about my setup, please send a direct message. I can also go into much deeper interest in a DM.
 

Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #139 on: August 19, 2022, 01:00:12 pm »
Interesting why SCOA=SCOB=SCOC=SCOD?
SS_BI(pin 73) on ALL adapter connected to pulldown. I think you mislabeled, that pin is BV(pin71) and will be similar to my waveform.

TL;DR I think that the pin indicated in the rectangular diagram is incorrect.
According to the diagram "SS" is pin 73, but according to the more recent schematic of the adapter (and work with my EPM7064 emulation) it is pin 77.

I am now very familiar with the waveforms needed by the EPM7032.

SS is needed in order to get good data on SCOA/B. So I am pretty certain that if your device is wired to the programmer correctly you will see a waveform on "SS_BI".

SCOA/B is unloaded 16 bits at a time using the SK clock. For the first bit (of 16) SS is LOW, then it is HIGH for the next 15. At the end of every 16 SK clocks SCK is pulses (I sort of guess that this loads the next 16 bits into the output shift register).

I am making the assumption (and I could be wrong) that the behaviour of SS_BI for the 7064 will be the same as the behaviour of SS for the 7032. I think that I have now confirmed this from the EPM7064 emulation, however there is still confusion as to which is the SS pin on the device, since the source documents differ and/or are incomplete.
 

Offline pityokas

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #140 on: August 19, 2022, 02:08:29 pm »
All SCO outputs are the same because this is a trace from an emulated EPM7064.
Maybe wrong emulated?
On my waveform SCOA!=SCOB!=
The first 2 byte come from SCOA, the second from SCOB ....

Quote
How to make this compatible with Pulseview - I have no idea.
Binary file. byte after byte, that's all.

Quote
I am very happy with these waveform traces for the EPM7032. This is way I am CERTAIN than your SS waveform is incorrect.
On EPM7032?

Quote
SS is needed in order to get good data on SCOA/B. So I am pretty certain that if your device is wired to the programmer correctly you will see a waveform on "SS_BI".
SS is input or output for EPM?

 

Offline pityokas

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #141 on: August 21, 2022, 08:20:56 am »
Another read of EPM7032S-44 but this time with Topmax.
This is very close to your waveform, I think bee sending the reading address pointer every time, and ALL and maybe others just clock SCK once.
There are some spikes including on GND there are very short, just ignore, probably connected the GND to wrong place.
 

Offline pityokas

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #142 on: August 21, 2022, 10:24:37 am »
Attaching EPM7032S-44 erase/blank check waveform, nothing interesting, no commands, just static setup on pins.
 

Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #143 on: August 21, 2022, 03:55:01 pm »
Thank you for making the waveform traces @pityokas  :-+ When I first started this project (a year or two ago) I was hoping that someone who had access to genuine programmer hardware would be able to make traces of the pins, in order to allow the programming protocol top be reverse engineered.

Here is a quick summary of my findings for the EPM7032 with some guesses added.

The Vpp pin when taken to a high enough voltage (*) puts the device into test/programming mode, and the pins are configured into inputs and outputs for SK, SCL, SDIN, SDOUT, SCO, etc.

SDINA and SDINB are used to shift in 80 bits of data. For the read ID sequence to work, a pattern of 00001-00001-000001-00001-00001 (for 80 bits) is required. I have no idea of the significance of this pattern. Data on SDINA and SDINB is clocked in using the SCK clock.

The "set of 5" is also seen in the tables in the ALL03 programming software. This must tie in with the architecture in some way.

The ADDR pins (A6-A0) select a block of EEPROM memory. Since 160 bits are shifted in (80 on SDINA and 80 on SDINB) then we can guess that each block of EEPROM is 160 bits.

Address block 0x7C (hex) is a special block which contains the "read ID". I have no idea if this block is protected from erase or is simple implemented as ROM (rather than EEPROM).

Data is clocked out on SCOA and SCOB. I have a suspicions that these are the outputs of two 16 bit registers, as 16 bits are shifted out using SK, with a clock of SCK every 16 clocks of SK. For the first bit of SS is low and for the next 15 bits SS is high. An alternate interpretation is that SS must be low when SCK is clocked to load new data into the 16 bit SCO registers.

Each device type generates a different stream for read ID. For the EPM7032VLC-44 "V" 3.3V device the datastream of SCOA is 0146-8AAB-F533-6083-3643 (5 sets of 16 bits, with MSB clocked out first). This was observed on a genuine device and captured using a Rigol oscilloscope. The 80 bits for each SCO shifted out is unscrambled using an algorithm based around sets of 5 bits. When the 80 bits shifted out of SCOA are descrambled it becomes 10 bytes "0xFE 0x07 A L T E R A 9 3" (i.e. 10 * 8 bits = 80). The first two bytes define: Vpg - the programming voltage needed on Vpp (called Vpg in the ALL03 software); Tbe - time for bulk erase in ms (determined by a look up table) [note I am guessing the purpose based on the letters "BE"); and Tpg - time to program one EEPROM memory block (also determined using a look up table). The ALL03 software has hidden commands which can be enabled with the sequence "uIu" which gives the "I" command which prints the decoded read ID and Vpg, Tpg and tBe (see attachment).

NTPW is the pin used for the programming and erase pulse. While Vpp/Vpg is high (12V or so) this pin MUST be '1'. It is pulsed LOW for between 20 to 500ms (depending upon device) to either program a block of EEPROM as addressed using the ADDR pins, or to erase everything. Of course it should only be taken low when the appropriate sequence has been applied to other pins.

the ADDR pins (A6-A0) select the block of EEPROM to be programmed or read back. When programming a block of EEPROM the data to be programmed is shifted in on SDINA and SDINB. When reading back a block it is the same as the "read ID " waveforms except that the ADDR pins select the block of EEPROM to be read. For blank check all EEPROM address blocks are read back and all 160 bits (80 from SCOA and 80 from SCOB) must be '1' to confirm the erased state. In the ALL03 blank check command address blocks 0 to 0x57 (87 decimal) are read back in order, then the next few blocks are not read sequentially but goes to 0x68 with the final two reads of address blocks 0x70 and 0x71. This is 106 address blocks in total or 2.21k bytes of data.

The ALL03 software reads in the data to be programmed in POF format. Using Altera Quartus 13.0 (free download) it is possible to create a POF for the MAX7000. My only concern is that the POF format might be different for different versions of the chip A,B,s (JTAG). I compiled a very simple piece of verilog code which simply routine pin 4 to pin 5 (no clocks or flops were used). The data portion of the POF file (having removed the head) was approx 1900 bytes. I do not know the data format, however the  size of the header can vary and contains textual information.



(*) for the EPM7032VLC-44 which is the "V" 3.3V Vcc device, I only needed to raise Vpp to 5.5V in order to enable test/programming mode and unload the read ID data stream (on a real device). Note: for programming or erase the required Vpp will be around 12V, the exact needed value is encoded into the read ID data stream.

In my DOSBOX-X emulation of the ALL03 ISA card, ALL03 registers, and EPM7032 device, I added emulation for the SCOA and SCOB data streams for the "read ID" sequence. I was able to use the ALL03 software to confirm that the data steams were correct, since when unscrabled the magic string "ALTERA93" appears. The emulation of the "read ID" is important, otherwise the software will not generate any further waveform stimulus unless a device has been detected via the "read ID" data stream mechanism.
 

Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #144 on: August 21, 2022, 05:46:33 pm »
Request.

Does anyone have the Altera MAX+Plus II software? I believe that this software requires a license and possible uses a dongle for protection too.

Would it be possible to create some POF files for each of the EPM7032 devices which it supports?

I would like to look at the files to determine the size of the data section of this file, to see if it is the same or different length to the POF file created by the Quartus II 13.0 software which I am using.

The POF generated for the supported device EPM7032AE has a data section of 1901 bytes.
 

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Offline Beta_vulgaris

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #146 on: August 21, 2022, 06:29:40 pm »
Does anyone have the Altera MAX+Plus II software?
I am working on cross-annotating this software, based on the Solaris version (with symbol table, Ghidra decompiler) and Windows (for debugging, Hex-Rays decompiler) MAX+plus 7.2 (available on the Internet Archive). I can upload the application and annotations if we need.
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Offline Beta_vulgaris

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #147 on: August 21, 2022, 06:41:11 pm »
I do not know the data format, however the  size of the header can vary and contains textual information.
Microchip(Atmel) POF2JED can output some debugging information to dump.txt, see whitequark's Twitter. I can upload the modified executable, too.
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Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #148 on: August 21, 2022, 07:07:19 pm »
Does anyone have the Altera MAX+Plus II software?
I am working on cross-annotating this software, based on the Solaris version (with symbol table, Ghidra decompiler) and Windows (for debugging, Hex-Rays decompiler) MAX+plus 7.2 (available on the Internet Archive). I can upload the application and annotations if we need.

If you have the chance to create a POF from a simple project for the EPM7032, it would be useful to know if the format as the same as generated by the Quartus software (which I would prefer to use).

I will take a look at the v7.2. I will be interested to see what level of capability it has (without licence?). I'm not sure which version of Windows it will work under ????

I did a quick experiment using Quartus II 13.0, generating some POFs from a trivial Verilog source.

EPM7032AELC44 - data length = 1901
EPM7032BTC44 - data length = 1945
EPM7032SLC44 - data length = 1892 (the S device has a modified architecture as compared to the non-S, so the smaller POF data section was a surprise).


 

Offline migryTopic starter

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Re: Programming (non-JTAG) MAX7000 devices
« Reply #149 on: August 21, 2022, 07:18:01 pm »
I do not know the data format, however the  size of the header can vary and contains textual information.
Microchip(Atmel) POF2JED can output some debugging information to dump.txt, see whitequark's Twitter. I can upload the modified executable, too.

I wrote something quick and dirty using the Perl language. If you have a POF please try it and let me know. It is incomplete.

NOTE: I cannot upload files ending dot PL, so I renamed it to dot BAS. I am sure you can figure out what to do if you need to run it. Requires Perl.
 


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